Hardware Overview

Purpose and Scope

Quantum hardware is the physical system, control apparatus, measurement chain, and classical feedback stack that realize an information-processing task. A platform is therefore more than a material and more than a list of qubits. It must connect a declared logical operation to a reproducible physical procedure:

$$\begin{aligned} \text{task} &\longrightarrow \text{encoding} \\ &\longrightarrow \text{control} \\ &\longrightarrow \text{measurement} \\ &\longrightarrow \text{validated output}. \end{aligned}$$

This page supplies a platform-neutral language for making that connection. It compares platform families by physical degree of freedom, encoding, initialization, native control, readout, error structure, connectivity, cycle time, infrastructure, scaling architecture, and network compatibility. It deliberately does not name a winner. The best architecture depends on the task, error-correcting code, scale, accuracy target, operating environment, and date of comparison.

The scope is architecture-level quantum information. Josephson Effect owns the condensed-matter basis of superconducting circuits. Ion Traps, Optical Tweezers, and Rydberg Atoms own the underlying AMO physics. Quantum Channels and Noise owns the general channel theory. The present page asks how those ingredients constrain a processor, simulator, sensor, memory, or network node.

A Hardware Platform Is an Operational Contract

A physical device generally has a Hilbert space larger than the intended computational space. Let $P$ project onto the code or computational subspace $\mathcal H_{\mathrm{comp}}$. Then

$$\begin{aligned} \mathcal H_{\mathrm{phys}} &= \mathcal H_{\mathrm{comp}} \oplus \mathcal H_{\mathrm{leak}}, \\ P &: \mathcal H_{\mathrm{phys}} \to \mathcal H_{\mathrm{comp}}. \end{aligned}$$

For an encoded qubit, two orthogonal states in $\mathcal H_{\mathrm{comp}}$ are identified as $\lvert 0\rangle$ and $\lvert 1\rangle$. They may be atomic hyperfine levels, low-lying eigenstates of a nonlinear circuit, spin states in a quantum dot, optical paths, photon-number superpositions, or collective fusion degrees of freedom. The labels alone say nothing about how the states are prepared, transformed, or measured.

A controlled device can be represented schematically by

$$H(t) = H_0 + \sum_k u_k(t)H_k,$$

where $H_0$ is the drift Hamiltonian, the $H_k$ are available control generators, and $u_k(t)$ are classical waveforms. A gate claim must identify the implemented channel, not merely the intended unitary. If $\mathcal E_u$ is the physical channel generated by a pulse sequence and $\mathcal U(\rho)=U\rho U^\dagger$ is the target, characterization asks how close $\mathcal E_u$ is to $\mathcal U$ on the relevant inputs and under simultaneous operation.

Readout is likewise a physical process. A measurement with outcomes $m$ is described by a POVM $\{M_m\}$,

$$p(m\mid \rho) = \operatorname{Tr}(M_m\rho), \qquad \sum_m M_m=I.$$

Detector response, assignment error, loss, dark counts, state disturbance, latency, and reset all belong to the hardware contract. A processor that performs excellent coherent gates but cannot measure and reset quickly enough for error correction may be poorly matched to a fault-tolerant architecture.

Leakage illustrates why the full physical space matters. After a process $\mathcal E$,

$$L(\rho) = 1-\operatorname{Tr}\!\left[ P\,\mathcal E(\rho) \right]$$

is the probability outside the declared computational subspace. Leakage is not generally equivalent to an ordinary Pauli error: it can persist across cycles, corrupt neighboring operations, and evade a decoder that assumes every carrier remains a qubit.

A hardware result rests on three coupled layers. Logical requirements determine operations and error targets; the device layer supplies an encoding, native controls, connectivity, readout, and reset; infrastructure makes those operations stable and repeatable. Calibration and feedback close the loop. A qubit count describes only one small part of this contract.

Requirements Shared Across Platforms

DiVincenzo’s criteria remain a useful starting point: a scalable, well-characterized quantum system; initialization; coherence long compared with gate time; a universal gate set; and qubit-specific measurement, with additional requirements for converting stationary and flying qubits and transmitting flying qubits. Modern architectures refine this list because error correction, calibration, and systems engineering cannot be left implicit.

A credible general-purpose architecture must address:

1. Physical carrier and encoding. What degree of freedom stores information, what larger levels exist, and how reproducibly can units be fabricated or assembled?
2. Initialization and entropy removal. How are fresh low-entropy states supplied, and at what rate can measured or corrupted carriers be reset?
3. Controllability. Which one-body and entangling interactions are native? Which logical operations require compilation, ancillas, measurement, or probabilistic heralding?
4. Measurement. What is observed, with what fidelity and latency, and is the readout destructive, quantum non-demolition, number resolving, or heralded?
5. Error structure. What are the strengths, correlations, time dependence, leakage pathways, erasures, loss mechanisms, and coherent components of the noise?
6. Connectivity and motion. Which pairs can interact directly? Can information carriers, couplers, photons, or interaction zones be routed?
7. Parallel operation. Which controls and measurements remain accurate when many operations run simultaneously?
8. Fault-tolerant compatibility. Can the platform execute repeated syndrome cycles, feed a decoder, and suppress logical error as code distance grows?
9. Classical support. Can waveform generation, discrimination, decoding, scheduling, calibration, and feedback keep pace with the quantum cycle?
10. Scalable infrastructure. How do wiring, heat load, lasers, vacuum, optics, detectors, fabrication yield, packaging, and maintenance scale?
11. Modularity and networking. Can quantum states be transferred between processing regions or converted to a low-loss carrier without destroying their coherence?

Meeting each item once in a laboratory is not the same as meeting all of them simultaneously, repeatedly, and at scale.

Compare a Task at a Declared Layer

There is no layer-independent hardware score. At least four layers should be separated:

Layer	Representative object	Appropriate question
physical component	junction, ion, atom, emitter, cavity, detector	does one component exhibit the needed transition, lifetime, coupling, or efficiency?
physical operation	preparation, gate, transport, readout, reset	what channel is implemented under realistic simultaneous operation?
encoded or logical operation	syndrome round, logical memory, logical gate	does increasing code size suppress the relevant logical failure probability?
application workflow	algorithm, simulation, sensing, networking task	what answer is produced at stated accuracy, latency, throughput, and total resource cost?

A long single-qubit coherence time belongs to the first layer. A low average two-qubit gate error belongs to the second. A below-threshold memory experiment belongs to the third. A useful chemistry estimate or distributed entanglement service belongs to the fourth. None can be substituted for another.

The comparison must also fix the task. A fast, locally connected processor may suit repeated surface-code cycles. A slower platform with long-lived qubits and flexible connectivity may reduce routing overhead. Photons may be natural communication carriers even when stationary memories are needed for storage. Oscillator encodings may reduce one kind of correction overhead while demanding high-quality ancilla control. These are architectural tradeoffs, not a total order.

Metrics Need Denominators and Context

Metrics for Quantum Hardware is the canonical home for formulas, characterization protocols, uncertainty, and reporting requirements. The definitions below are the minimum needed to interpret the platform comparison.

Coherence and operation time

$T_1$ describes energy relaxation for a specified transition and environment. $T_2$ describes decay of phase coherence for a specified experiment; in a two-level Markovian model,

$$\frac{1}{T_2} = \frac{1}{2T_1} + \frac{1}{T_\phi},$$

where $T_\phi$ is a pure-dephasing time. Real devices can show nonexponential decay, drift, low-frequency noise, or pulse-sequence-dependent coherence.

The ratio

$$Q_{\mathrm{op}} = \frac{T_2}{t_{\mathrm{op}}}$$

is an informative timescale ratio, but it is not the number of gates that can be executed successfully. It omits relaxation during other operations, control error, crosstalk, leakage, idle error, measurement, reset, and correlated failures.

Gate fidelity

For a $d$-dimensional computational space, the average gate fidelity is

$$F_{\mathrm{avg}}(\mathcal E,U) = \int d\psi\, \langle\psi\rvert U^\dagger \mathcal E(\lvert\psi\rangle\langle\psi\rvert) U \lvert\psi\rangle.$$

The average infidelity $r=1-F_{\mathrm{avg}}$ compresses a channel into one number. Equal values of $r$ can hide very different behavior: stochastic, coherent, biased, correlated, non-Markovian, or leakage errors. The characterization protocol also matters. Randomized benchmarking, cycle benchmarking, process tomography, and application-level tests answer different questions and carry different assumptions.

Readout and initialization

For binary readout, an assignment matrix can be written

$$A = \begin{pmatrix} p(0\mid 0) & p(0\mid 1)\\ p(1\mid 0) & p(1\mid 1) \end{pmatrix}.$$

The mean assignment fidelity

$$F_{\mathrm{assign}} = \frac{ p(0\mid 0)+p(1\mid 1) }{2}$$

does not by itself describe quantum non-demolition behavior, leakage discrimination, crosstalk, time cost, detector dead time, or whether the prepared reference states were accurate. State-preparation-and-measurement error should not casually be labeled readout error.

Connectivity, parallelism, and latency

Represent direct entangling capability by a graph $G=(V,E)$. Its degree, diameter, geometry, dynamic reconfigurability, and edge quality influence routing cost. Yet a connectivity graph is incomplete without a conflict graph specifying which nominally available operations can run at the same time without unacceptable crosstalk.

Cycle time includes more than gate duration:

$$\begin{aligned} t_{\mathrm{cycle}} &= t_{\mathrm{prepare}} + t_{\mathrm{control}} + t_{\mathrm{measure}} \\ &\quad + t_{\mathrm{decode}} + t_{\mathrm{feedback}}, \end{aligned}$$

with overlaps stated explicitly. A slower gate can still participate in a competitive architecture when operations parallelize well and coherence is long. A fast gate can be less useful when readout, reset, routing, or classical latency dominates.

Error per cycle and logical error

The quantity most closely connected to a fault-tolerant computation is a logical failure probability for a declared code, circuit, decoder, noise process, and cycle. In an idealized below-threshold regime one often encounters a scaling model of the form

$$p_{\mathrm L}(d) \approx A \left( \frac{p}{p_{\mathrm{th}}} \right)^{(d+1)/2},$$

for odd code distance $d$. This is not a universal law. The constants and even the usefulness of one physical error rate $p$ depend on leakage, bias, erasures, correlations, decoding, boundaries, and circuit details. Surface Code develops the canonical code-specific interpretation.

Platform Families

The following sketches identify architectural mechanisms, not current record values. Record fidelities, qubit counts, and vendor roadmaps change rapidly and should be checked against dated primary sources.

Superconducting circuits

Superconducting platforms use quantized electrical modes built from capacitors, inductors, resonators, and Josephson junctions. Transmons encode a qubit in the lowest two levels of a weakly anharmonic circuit; fluxonium and other designs reshape the spectrum and noise sensitivity. Microwave drives provide single-qubit control. Capacitive, inductive, resonator-mediated, or tunable couplings provide entangling gates, while dispersive circuit-QED measurement maps qubit state to a microwave field.

Their architecture supports fast control, chip fabrication, integrated resonators, and repeated measurement cycles. Typical layouts have local or engineered graph connectivity. Central challenges include dielectric and interface loss, quasiparticles, flux and charge noise, frequency crowding, leakage, crosstalk, calibration drift, packaging, cryogenic wiring, and the heat and bandwidth budget of control electronics. Microwave photons are convenient on chip but lossy at room-temperature interfaces, so long-distance links require conversion or another carrier.

Circuit QED Overview owns the light–matter architecture, Circuit QED owns its open-system treatment, and Josephson Effect owns the nonlinear circuit element.

Trapped ions

Trapped-ion qubits use long-lived internal electronic, hyperfine, or optical states of atomic ions confined by electromagnetic fields in ultrahigh vacuum. Optical pumping initializes the ions; state-dependent fluorescence provides high-contrast readout. Laser or microwave fields implement one-qubit rotations, and shared motional modes mediate entangling gates.

Ions within one register can have flexible or effectively all-to-all interaction graphs, reducing some routing costs. The same collective motion creates scaling constraints through mode crowding, heating, spectral complexity, and control calibration. Larger architectures investigate segmented traps, ion shuttling, multiple zones, sympathetic cooling, and photonic links between modules. Gate and measurement cycles are usually longer than superconducting microwave cycles, while internal-state coherence can be much longer. Vacuum hardware, stable lasers, optical access, motional control, and low-latency orchestration are part of the system.

Trapped-Ion Qubits owns the architecture-level account of encodings, reachability, QCCD routing, photonic modules, and scaling. Ion Traps explains confinement and normal modes; Trapped-Ion Control develops sidebands, cooling, gates, and readout; Trapped Ions treats measurement and dissipation.

Neutral atoms and Rydberg arrays

Neutral-atom processors encode information in atomic ground, clock, hyperfine, or Rydberg-coupled states. Optical tweezers can assemble and rearrange large two- or three-dimensional arrays. One-qubit operations use optical or microwave fields; strong Rydberg interactions enable blockade-based entangling gates and analog many-body Hamiltonians. Fluorescence imaging usually supplies readout.

The platform combines identical atomic carriers, reconfigurable geometry, parallel control, and direct access to analog simulation. Important errors include atom loss, imperfect loading and rearrangement, laser phase and intensity noise, Doppler effects, spontaneous emission, Rydberg-state decay, addressing crosstalk, and motion induced by control. Atom loss can sometimes be identified as an erasure, which is more informative than an unlocated error, but only when the measurement record reliably distinguishes it. Scalable operation also requires vacuum, laser delivery, imaging, calibration, and repeated reload or replacement strategies.

Neutral-Atom and Rydberg Qubits owns the architecture-level account of loading, storage, reconfigurable geometry, digital gates, analog operation, loss-aware processing, and scaling. Optical Tweezers, Rydberg Atoms, and Rydberg Blockade own the underlying physics. Neutral Atoms owns platform-specific open-system effects.

Photonic platforms

Photonic quantum information can use polarization, path, time-bin, frequency-bin, photon number, or continuous field quadratures. Sources prepare single photons, squeezed states, or entangled resource states; interferometers and phase shifters implement linear transformations; nonlinear interactions or measurement-induced operations supply non-Gaussian or entangling resources; photodetectors provide measurement.

Photons propagate well and naturally connect remote nodes. They interact weakly with the environment during transmission, but that same weak interaction makes deterministic two-photon gates difficult. Loss, source brightness and purity, indistinguishability, mode matching, switching, detector efficiency, dark counts, feedforward latency, and large interferometric networks are central constraints. Some architectures trade deterministic matter-qubit gates for probabilistic fusion operations on cluster states; their resource accounting must include source attempts, multiplexing, heralding probability, discarded events, and detector load. Room-temperature optical propagation does not mean the full system is room temperature: high-performance sources and detectors may require cryogenic support.

Photonic Qubits owns the architecture-level account of encodings, source-to-detector accounting, linear-optical processing, cluster and fusion models, loss, feed-forward, and network interfaces. Quantized Electromagnetic Modes, Beam Splitters, Parametric Down-Conversion, and Photon Counting supply the canonical optical physics.

Semiconductor spin qubits

Semiconductor platforms encode qubits in electron or nuclear spins associated with quantum dots, donors, or related confined structures. Initialization and readout often use spin-selective tunneling and spin-to-charge conversion. Magnetic resonance, electric-dipole spin resonance, exchange interactions, capacitive couplers, and microwave resonators provide control and coupling.

Their small physical footprint and potential relation to semiconductor fabrication motivate dense arrays and cryogenic classical integration. The same density creates severe requirements on material purity, electrostatic uniformity, gate wiring, tuning, charge-noise control, thermal budget, and variability. Nearest-neighbor exchange can be fast but demands routing, shuttling, long-range couplers, or modular links. Isotopic purification can reduce nuclear-spin noise; interfaces, valley structure, charge admixture, and fabrication disorder remain architecture-specific concerns.

Silicon Spin Qubits owns the architecture-level account of gate-defined dots, donor registers, encodings, exchange gates, shuttling, cryogenic control, manufacturing, and logical evidence. Spin Qubits develops representative dephasing and relaxation models. Quantum Matter owns the semiconductor and mesoscopic material basis.

Defect and solid-state spin platforms

Color centers and other defects host electronic and nuclear spins in solids such as diamond and silicon carbide. Microwave or optical fields control the spin; optical cycling transitions can initialize and read it; nearby nuclear spins may act as memories. Some defects operate coherently at comparatively high temperatures, while indistinguishable optical emission and network protocols can demand cryogenic operation.

These systems are attractive for sensing, quantum memory, and optically connected nodes. Their challenges include deterministic defect placement, spectral inhomogeneity, charge-state stability, photon collection, spin–photon interface efficiency, material surfaces, strain, and scalable nanophotonics. A long isolated-spin coherence time does not automatically yield a high-rate network node: collection probability, optical indistinguishability, heralding rate, memory lifetime under repeated attempts, and local gate quality must be combined.

Defect and Solid-State Spin Qubits owns the architecture-level account of hybrid electron–nuclear registers, spin–photon interfaces, heralded links, fabrication, and dated system evidence. NV Centers and Solid-State Defects owns their representative open-system physics and sensing noise.

Bosonic encodings

A bosonic qubit stores logical information in a subspace of one oscillator rather than in one physical two-level carrier. Cat, binomial, rotation-symmetric, and Gottesman–Kitaev–Preskill encodings distribute information across number or phase space so that dominant oscillator errors acquire detectable structure. The oscillator may be microwave, optical, acoustic, or mechanical; an ancillary nonlinear system usually supplies control and syndrome extraction.

Bosonic encoding is therefore an architectural layer that can be combined with several substrates, not a mutually exclusive material platform. Its appeal is hardware-efficient error correction and the possibility of noise bias or autonomous protection. Its costs include demanding state preparation, ancilla-induced errors, oscillator loss, non-Gaussian control, leakage outside the chosen manifold, and the need to compare an encoded oscillator fairly with an encoded register of two-level systems.

Bosonic Qubits owns the architecture-level account of complete oscillator modules, code-family hardware implications, nonlinear control, active and autonomous correction, break-even evidence, and full resource accounting.

Continuous-variable platforms

Continuous-variable architectures process field quadratures rather than first truncating each mode to a qubit. Gaussian states and operations, linear optics, squeezing, displacement, homodyne detection, and feedforward can be efficient and sometimes deterministic. Universal quantum computation requires an appropriate non-Gaussian resource, while fault tolerance additionally requires finite-energy encodings and error correction.

The natural metrics differ from qubit platforms: squeezing, optical loss, detector efficiency, mode purity, bandwidth, clock rate, and non-Gaussian resource quality can matter more than a two-qubit gate fidelity. A quoted squeezing level does not alone establish logical fault tolerance because finite squeezing appears as displacement noise and propagates through the full preparation and correction circuit.

Continuous-Variable Platforms develops the optical and microwave implementations, mode graphs, nonlinear resource boundary, end-to-end loss ledger, and dated hardware evidence.

Quantum memories as a subsystem

A quantum memory may use an atomic ensemble, a single spin or small register, an oscillator, a photonic loop, or an actively corrected logical encoding. Memory is therefore an interface role rather than an exclusive carrier family. A useful device must accept a declared input ensemble, preserve it for a declared interval, and return it on demand or according to a stated timing contract. Coherence time alone omits write and read efficiency, conditional fidelity, background, bandwidth, mode capacity, latency, reset, and duty cycle.

Quantum Memories owns the hardware-neutral write–store–read channel, technology comparison, network-timing interface, performance vector, and dated evidence audit. Electromagnetically Induced Transparency retains the canonical dark-state-polariton derivation for one important optical-memory mechanism.

Topological proposals

Topological quantum computation seeks to encode information nonlocally in fusion spaces or parity sectors so that local perturbations have limited access to the logical state. Non-Abelian anyons, Majorana zero modes, braiding, fusion measurement, and measurement-only protocols supply the conceptual ingredients. If a suitable phase is prepared and controlled, parts of an operation could receive protection from topology.

The status labels must remain separate:

• Established theory: topological order, anyon models, and fault-tolerant constructions under explicit assumptions.
• Established phases and excitations: experimentally supported topological phases or quasiparticle phenomena in specified systems.
• Proposed qubit implementation: a mapping from candidate modes and controls to an encoded qubit and gate set.
• Experimental signature: evidence consistent with part of that proposal, subject to alternative explanations and device-specific systematics.
• Scalable protected architecture: a demonstrated path including initialization, braiding or equivalent control, readout, non-Clifford resources, error correction, and scaling.

Evidence at one level does not prove the next. In particular, a spectroscopic or transport signature associated with a candidate Majorana mode is not by itself a protected logical qubit, and a protected Clifford operation is not by itself a universal architecture. Topological Qubits owns the complete module, parity-control, error, metric, resource, and dated hardware-evidence ledgers. Topology in Quantum Matter owns the phase concepts; Anyons and Braiding and Topological Quantum Computation Bridge develop the physics-to-information bridge.

A Qualitative Comparison

The table records typical architectural tendencies. Individual devices can depart substantially from them.

Platform family	Encoding and native interaction	Connectivity and cycle character	Characteristic infrastructure	Network interface	Representative bottlenecks
superconducting circuits	circuit eigenstates; microwave-driven and tunable interactions	usually local engineered graphs; fast repeated cycles	dilution refrigeration, microwave wiring, packaging, cryogenic control	microwave links; optical conversion is nontrivial	material loss, leakage, crosstalk, frequency crowding, cryogenic scaling
trapped ions	internal states; motion-mediated entanglement	flexible within a register; slower gates and readout	ultrahigh vacuum, stable lasers or microwaves, precision traps	optical emission and heralded photonic links	mode complexity, heating, laser stability, shuttling and modular rate
neutral atoms	internal states; Rydberg interactions	reconfigurable arrays and parallel zones	vacuum, tweezer and control lasers, imaging	optical transitions, cavities, or converted photons	loss, loading, motion, Rydberg decay, addressing and readout
photonics	discrete optical modes or quadratures; interference, measurement, and nonlinear resources	routing-rich and naturally distributed; often probabilistic or cluster based	sources, interferometers, switches, detectors, stabilization	native low-loss optical carrier	loss, indistinguishability, source and detector efficiency, feedforward
semiconductor spins	electron or nuclear spins; exchange, capacitive, or resonator coupling	dense mostly local arrays; fast electrical control varies by design	cryogenic semiconductor devices and dense wiring	microwave resonators or optical interfaces in selected systems	variability, charge noise, tuning, routing, cryogenic electronics
solid-state defects	electronic and nuclear spins; local gates and spin–photon coupling	local registers with photonic modular links	material growth, nanophotonics, optical and microwave control	often an optical transition	placement, spectral spread, collection, interface efficiency
bosonic encodings	oscillator codewords; ancilla-mediated nonlinear control	substrate dependent; one mode can hold one encoded qubit	high-quality modes plus ancilla and control stack	substrate dependent	state preparation, loss, ancilla faults, fair resource accounting
continuous variable	field quadratures; Gaussian optics plus non-Gaussian resources	high-bandwidth multimode networks	squeezing, interferometry, homodyne, fast feedforward	native optical or microwave modes	finite squeezing, loss, non-Gaussian resources, mode management
topological proposals	nonlocal fusion or parity sectors; braiding or measurement	proposal dependent	topological materials or engineered simulators plus control/readout	proposal dependent	phase identification, controllable operations, universality, scalable evidence

The absence of numerical rankings is intentional. A number without a common protocol, workload, confidence interval, simultaneous-operation condition, and date creates false precision.

Worked Example: One Logical Interaction, Different Hardware Costs

Suppose a compiled circuit requires a controlled operation between logical qubits $a$ and $b$. The abstract Circuit Model records one two-qubit gate. Hardware cost depends on the native interaction graph and encoding.

On a nearest-neighbor line

$$a - q_1 - q_2 - b,$$

one option is to route states using SWAP operations, perform the gate, and possibly restore the mapping. If each SWAP is compiled into three controlled-NOT gates, routing can dominate the original operation. A compiler may instead maintain a changing logical-to-physical map and avoid restoring it.

In an ion register, a shared motional bus may permit a direct pair interaction, but the pulse duration and error depend on spectral crowding, mode occupation, and simultaneous gates. In a neutral-atom array, atoms may be moved or a Rydberg interaction zone may be selected, trading routing gates for transport, recooling, or reconfiguration time. In a photonic cluster-state architecture, the corresponding logical operation may be enacted by measurements on a prebuilt resource state, shifting cost into source attempts, fusion success, multiplexing, and feedforward.

Therefore the meaningful resource record is not simply “one controlled gate.” It is

$$\begin{aligned} R = \bigl(& N_{\mathrm{phys}}, N_{\mathrm{ent}}, D, t_{\mathrm{wall}}, \\ & N_{\mathrm{shots}}, p_{\mathrm{success}}, p_{\mathrm L}, R_{\mathrm{classical}} \bigr), \end{aligned}$$

with each component defined. Here $D$ is scheduled depth and $R_{\mathrm{classical}}$ includes compilation, decoding, calibration, and feedback resources. Different architectures can minimize different components.

Error Structure Can Reverse a Ranking

Two devices with the same average infidelity need not have the same logical performance. Consider three simplified channels with comparable mean error:

1. independent depolarizing faults;
2. dephasing strongly biased toward $Z$ errors;
3. located loss events reported as erasures.

A code and decoder adapted to bias can exploit the second model. An erasure decoder can exploit known error locations in the third. Conversely, coherent over-rotations or long-range correlated faults can accumulate more severely than a stochastic model inferred from one average number. Leakage can create time correlations because a leaked carrier remains outside the code space.

This is why Noise in Quantum Information distinguishes mechanism, channel representation, memory, locality, and identifiability. Hardware comparison should carry enough of that structure into the code-level simulation. “Below one percent” is not an error model.

Scaling Is a Systems Problem

Scaling a quantum processor changes the operating problem. It is not generally achieved by repeating an isolated qubit unchanged.

Fabrication or assembly

Solid-state devices face yield, parameter spread, interfaces, packaging, and repairability. Atomic systems benefit from intrinsically identical particles but must load, cool, arrange, retain, and address them. Photonic systems must combine many sources, modes, switches, and detectors with stable indistinguishability. A scalable architecture needs a strategy for missing or defective components, not merely a perfect unit cell.

Control fan-out

Independent control lines, beams, frequencies, or spatial light patterns consume room, bandwidth, power, and calibration effort. Multiplexing reduces fan-out but may reduce selectivity or increase crosstalk. Cryogenic processors must respect thermal loads. Laser-based systems must distribute phase-stable light. Photonic systems must stabilize large interferometers and synchronize sources and detectors.

Calibration and drift

Let $\theta(t)$ denote device parameters and $u^\star(\theta)$ a calibrated control. Drift produces a mismatch

$$\delta u(t) = u^\star\!\left(\theta(t_0)\right) - u^\star\!\left(\theta(t)\right).$$

As the system grows, exhaustive recalibration can become too slow. Scalable operation therefore requires observability of drift, local or hierarchical calibration, automation, uncertainty tracking, and schedules that do not invalidate one calibration while improving another.

Classical real-time support

Fault-tolerant operation requires measurement discrimination, decoding, conditional control, and data movement on a deadline. The relevant latency is the closed loop from analog detector signal to an accepted control decision. A decoder that is accurate but falls progressively behind the syndrome stream is not an online decoder.

Maintenance and availability

Scientific usefulness depends on uptime, reproducibility, calibration age, failed-component handling, and throughput. Peak fidelity from a selected interval can coexist with poor daily availability. Hardware reports should separate best-case records from sustained system behavior.

Modularity and Interconnects

No single module must necessarily contain the whole computer. Modular architectures connect smaller registers with transported matter qubits, microwave buses, optical photons, or transducers. A heralded remote-entanglement link with success probability $p_{\mathrm{link}}$ per independent attempt has mean attempt count

$$\mathbb E[N] = \frac{1}{p_{\mathrm{link}}}.$$

If attempts occur every $\tau$ and all overheads are ignored, the mean generation time is $\tau/p_{\mathrm{link}}$. Real links add detector dead time, memory decoherence, multiplexing, purification, routing, and classical acknowledgment. Network compatibility therefore includes wavelength, bandwidth, collection efficiency, indistinguishability, conversion noise, memory lifetime, and protocol rate.

Transduction can connect otherwise incompatible carriers, such as microwave and optical photons, but conversion efficiency alone is insufficient. Added noise, bandwidth, pump-induced heating, bidirectionality, and preservation of quantum correlations must be measured. Interconnects and Transduction owns the complete accepted-input-to-usable-output link contract, including deterministic transfer, heralded entanglement, carrier conversion, temporal modes, and end-to-end evidence. A modular architecture is attractive only when link errors and rates fit the logical protocol.

Modular Architectures owns the system-level composition problem: module roles and interfaces, topology and cut capacity, entanglement inventory, scheduling, distributed error correction, failure domains, and sustained availability.

How to Read a Hardware Claim

Before comparing two reported results, ask:

1. What physical object is counted: fabricated sites, occupied sites, calibrated qubits, simultaneously operated qubits, or logical qubits?
2. What operation, input ensemble, and metric were tested?
3. Was the result simultaneous across the processor or selected from individual best components?
4. What uncertainty, drift interval, and calibration age apply?
5. Are leakage, loss, postselection, heralding, and failed runs included?
6. Does “fidelity” mean state fidelity, process fidelity, average gate fidelity, assignment fidelity, entanglement fidelity, or application success?
7. What connectivity, parallelism, scheduling, and classical latency were available?
8. Is the comparison at physical, encoded, logical, or application level?
9. Does logical error decrease as code size increases under the same noise and decoding conditions?
10. What resource denominator is used: per gate, cycle, shot, successful event, logical operation, wall-clock second, or joule?
11. What classical baseline or competing architecture was evaluated, and on what date?
12. Which conclusion is directly measured, which is inferred through a model, and which is a projection?

A good report makes these answers reconstructible. A platform roadmap can motivate research, but it is not evidence that future milestones have been achieved.

Common Mistakes

• Ranking by qubit count alone. Count does not encode occupancy, connectivity, fidelity, leakage, readout, or logical performance.
• Dividing coherence time by gate time and calling the result circuit depth. This omits control error, parallel constraints, measurement, reset, idle periods, and correlations.
• Comparing record components from different operating modes. Best coherence, best gate, and best readout may not occur on the same device at the same time.
• Calling a gate native without stating its domain. A pulse can be native physically while the desired logical gate still needs echoes, routing, leakage reduction, or fault-tolerant gadgets.
• Treating all errors with equal average fidelity as equivalent. Bias, erasure information, coherence, correlation, and leakage change code performance.
• Equating material compatibility with manufacturing scalability. Fabrication heritage helps only if the quantum-specific yield, uniformity, packaging, control, and cryogenic requirements also scale.
• Equating identical atoms with a finished architecture. Loading, motion, optics, loss, and control fan-out remain.
• Equating optical transmission with a complete network. Sources, interfaces, memories, detectors, heralding, and rate are equally important.
• Calling a topological signature a topological qubit. Phase evidence, encoded state control, protected operations, and scalable architecture are separate claims.
• Using a hardware metric without a task. Every meaningful comparison needs an input, output, accuracy, and resource boundary.

Exercises

1. Compute leakage

A three-level device uses $\lvert0\rangle$ and $\lvert1\rangle$ as its qubit. After a pulse,

$$\rho = 0.48\lvert0\rangle\langle0\rvert + 0.49\lvert1\rangle\langle1\rvert + 0.03\lvert2\rangle\langle2\rvert.$$

Find the leakage probability.

Solution

With

$$P = \lvert0\rangle\langle0\rvert + \lvert1\rangle\langle1\rvert,$$

the computational population is

$$\operatorname{Tr}(P\rho) = 0.48+0.49 = 0.97.$$

Therefore $L=1-0.97=0.03$. The result identifies population outside the qubit subspace; it does not say whether the remaining qubit channel has coherent or stochastic error.

2. Audit a coherence ratio

A qubit has $T_2=200\,\mu\mathrm{s}$ and a nominal gate time $t_g=20\,\mathrm{ns}$. Calculate $T_2/t_g$ and explain why it is not a guaranteed executable depth.

Solution

Since $200\,\mu\mathrm{s}=200000\,\mathrm{ns}$,

$$\frac{T_2}{t_g} = \frac{200000}{20} = 10000.$$

This compares one measured coherence timescale with one gate duration. A circuit also accumulates relaxation, calibration error, crosstalk, leakage, idle error, routing, measurement, and reset costs. The $T_2$ experiment may not reproduce the noise spectrum during driven simultaneous operation. Thus $10000$ is a timescale ratio, not a depth guarantee.

3. Correct binary readout

Suppose

$$A = \begin{pmatrix} 0.98 & 0.07\\ 0.02 & 0.93 \end{pmatrix}, \qquad \mathbf f = \begin{pmatrix} 0.616\\ 0.384 \end{pmatrix},$$

where $\mathbf f=A\mathbf p$. Recover the estimated pre-readout probabilities $\mathbf p$.

Solution

The determinant is

$$\begin{aligned} \det A &= (0.98)(0.93) - (0.07)(0.02) \\ &= 0.91. \end{aligned}$$

Hence

$$A^{-1} = \frac{1}{0.91} \begin{pmatrix} 0.93 & -0.07\\ -0.02 & 0.98 \end{pmatrix}.$$

Multiplying gives

$$\mathbf p = A^{-1}\mathbf f = \begin{pmatrix} 0.60\\ 0.40 \end{pmatrix}.$$

This inversion corrects the calibrated classical assignment model. It does not remove preparation error, gate error, detector drift, or correlations absent from $A$.

4. Count routing gates

Four physical qubits form a line $a-q_1-q_2-b$. A simple strategy moves the state at $a$ next to $b$ using two SWAPs, applies one controlled-NOT, and then restores the original mapping with two SWAPs. If each SWAP costs three controlled-NOT gates, how many controlled-NOT gates are used?

Solution

There are four SWAPs in total, costing

$$4\times3=12$$

controlled-NOT gates. Including the desired controlled-NOT gives $13$. This is one compilation strategy, not a lower bound. A compiler can retain the changed mapping, use a different entangler, teleport information, or exploit hardware motion.

5. Compare cycle time

A syndrome cycle contains $1\,\mu\mathrm{s}$ of preparation, $4\,\mu\mathrm{s}$ of gates, $3\,\mu\mathrm{s}$ of measurement, $2\,\mu\mathrm{s}$ of decoding, and $1\,\mu\mathrm{s}$ of feedback. With no overlap, find the cycle time. If decoding overlaps completely with measurement, find it again.

Solution

Without overlap,

$$t_{\mathrm{cycle}} = 1+4+3+2+1 = 11\,\mu\mathrm{s}.$$

If the entire $2\,\mu\mathrm{s}$ decoding stage fits inside the $3\,\mu\mathrm{s}$ measurement interval,

$$t_{\mathrm{cycle}} = 1+4+\max(3,2)+1 = 9\,\mu\mathrm{s}.$$

A hardware report should state such overlap assumptions because summing component latencies can either overestimate or underestimate an implemented feedback loop.

6. Use an erasure flag

Two devices have the same total physical failure probability per operation. Device A reports the location of $80\%$ of its failures as reliable erasures. Device B produces only unlocated faults. Explain why equal total failure probability does not imply equal code performance.

Solution

An erasure flag supplies side information: the decoder knows where the affected carrier or operation is. It need not infer both error location and error type from the syndrome. Many codes consequently tolerate a larger rate of located erasures than unlocated faults. The remaining $20\%$ of Device A’s failures and any false or missed erasure flags still matter. A fair comparison must therefore pass the located and unlocated components, including correlations, into the same code and decoder model.

7. Estimate a heralded-link time

A modular link is attempted every $\tau=5\,\mu\mathrm{s}$ with independent success probability $p_{\mathrm{link}}=2\times10^{-3}$. Ignoring all other overhead, find the mean number of attempts and mean generation time.

Solution

For a geometric process,

$$\mathbb E[N] = \frac{1}{p_{\mathrm{link}}} = 500.$$

The mean time is

$$\mathbb E[t] = \frac{\tau}{p_{\mathrm{link}}} = 500(5\,\mu\mathrm{s}) = 2.5\,\mathrm{ms}.$$

Memory decoherence, reset, detector dead time, classical acknowledgment, and multiplexing would modify the operational rate.

8. Test below-threshold scaling

For a fixed code and decoder, measured logical failure probabilities per cycle are

$$\begin{aligned} p_{\mathrm L}(3) &= 2.0\times10^{-3}, \\ p_{\mathrm L}(5) &= 8.0\times10^{-4}, \\ p_{\mathrm L}(7) &= 1.1\times10^{-3}. \end{aligned}$$

Does this dataset show monotonic suppression through distance seven?

Solution

No. The failure probability decreases from distance three to five but increases from distance five to seven. The cause might be statistical uncertainty, finite-size effects, decoder mismatch, leakage, correlated noise, a changed circuit, or operation outside the asymptotic scaling regime. Error bars and identical experimental conditions are needed before interpreting the trend. One improved distance point does not establish sustained below-threshold scaling.

9. Classify platform claims

Classify each statement as a component, physical-operation, logical, or application-level claim:

1. “A resonator has a one-second lifetime.”
2. “A simultaneous two-qubit-gate experiment reports an average infidelity of $4\times10^{-3}$.”
3. “Logical memory error decreases from code distance three to seven.”
4. “A molecular energy is estimated to chemical accuracy in ten minutes.”

Solution

The statements are, respectively: component level, physical-operation level, logical level, and application level. Each can be valuable, but they support different conclusions. In particular, the component lifetime does not establish a logical memory, and the physical gate benchmark does not establish application accuracy without the remaining workflow.

10. Audit a “best hardware” statement

A press release says, “Platform X is the best quantum computer because it has the largest qubit count.” Write a minimal evidence request that would make the comparison scientifically interpretable.

Solution

Request a declared task and date; definitions of fabricated, active, calibrated, and logical qubits; connectivity and allowed parallel operations; preparation, gate, leakage, loss, readout, and reset characterization under simultaneous use; scheduled cycle time and uptime; a code and decoder if logical performance is claimed; uncertainty and postselection rules; total quantum and classical resources; and matched results for the comparison platforms. The evidence may establish an advantage for one workload and operating regime, but qubit count alone cannot establish a platform-wide ranking.

References

1. D. P. DiVincenzo, “The physical implementation of quantum computation,” Fortschritte der Physik 48, 771–783 (2000), doi:10.1002/1521-3978(200009)48:9/11<771::AID-PROP771>3.0.CO;2-E.
2. National Academies of Sciences, Engineering, and Medicine, Quantum Computing: Progress and Prospects (National Academies Press, 2019), doi:10.17226/25196.
3. J. Preskill, “Quantum computing in the NISQ era and beyond,” Quantum 2, 79 (2018), doi:10.22331/q-2018-08-06-79.
4. M. Kjaergaard et al., “Superconducting qubits: Current state of play,” Annual Review of Condensed Matter Physics 11, 369–395 (2020), doi:10.1146/annurev-conmatphys-031119-050605.
5. P. Krantz et al., “A quantum engineer’s guide to superconducting qubits,” Applied Physics Reviews 6, 021318 (2019), doi:10.1063/1.5089550.
6. C. D. Bruzewicz, J. Chiaverini, R. McConnell, and J. M. Sage, “Trapped-ion quantum computing: Progress and challenges,” Applied Physics Reviews 6, 021314 (2019), doi:10.1063/1.5088164.
7. C. Monroe and J. Kim, “Scaling the ion trap quantum processor,” Science 339, 1164–1169 (2013), doi:10.1126/science.1231298.
8. M. Saffman, “Quantum computing with atomic qubits and Rydberg interactions: Progress and challenges,” Journal of Physics B 49, 202001 (2016), doi:10.1088/0953-4075/49/20/202001.
9. M. Morgado and S. Whitlock, “Quantum simulation and computing with Rydberg-interacting qubits,” AVS Quantum Science 3, 023501 (2021), doi:10.1116/5.0036562.
10. J. Wang, F. Sciarrino, A. Laing, and M. G. Thompson, “Integrated photonic quantum technologies,” Nature Photonics 14, 273–284 (2020), doi:10.1038/s41566-019-0532-1.
11. J. L. O’Brien, “Optical quantum computing,” Science 318, 1567–1570 (2007), doi:10.1126/science.1142892.
12. G. Burkard, T. D. Ladd, A. Pan, J. M. Nichol, and J. R. Petta, “Semiconductor spin qubits,” Reviews of Modern Physics 95, 025003 (2023), doi:10.1103/RevModPhys.95.025003.
13. D. D. Awschalom, R. Hanson, J. Wrachtrup, and B. B. Zhou, “Quantum technologies with optically interfaced solid-state spins,” Nature Photonics 12, 516–527 (2018), doi:10.1038/s41566-018-0232-2.
14. A. Joshi, K. Noh, and Y. Y. Gao, “Quantum information processing with bosonic qubits in circuit QED,” Quantum Science and Technology 6, 033001 (2021), doi:10.1088/2058-9565/abe989.
15. C. Weedbrook et al., “Gaussian quantum information,” Reviews of Modern Physics 84, 621–669 (2012), doi:10.1103/RevModPhys.84.621.
16. C. Nayak, S. H. Simon, A. Stern, M. Freedman, and S. Das Sarma, “Non-Abelian anyons and topological quantum computation,” Reviews of Modern Physics 80, 1083–1159 (2008), doi:10.1103/RevModPhys.80.1083.
17. S. Das Sarma, M. Freedman, and C. Nayak, “Majorana zero modes and topological quantum computation,” npj Quantum Information 1, 15001 (2015), doi:10.1038/npjqi.2015.1.
18. M. H. Devoret and R. J. Schoelkopf, “Superconducting circuits for quantum information: An outlook,” Science 339, 1169–1174 (2013), doi:10.1126/science.1231930.
19. D. J. Reilly, “Engineering the quantum-classical interface of solid-state qubits,” npj Quantum Information 1, 15011 (2015), doi:10.1038/npjqi.2015.11.
20. G. Kurizki et al., “Quantum technologies with hybrid systems,” Proceedings of the National Academy of Sciences 112, 3866–3873 (2015), doi:10.1073/pnas.1419326112.

Further Connections

• Quantum Information and Computation places hardware beneath computation, communication, sensing, and simulation tasks without confusing the physical and logical layers.
• What Is Quantum Information? supplies the preparation–transformation–measurement language shared by every platform.
• Circuit Model distinguishes ideal gates, compiled gates, logical operations, and physical channels.
• Noise in Quantum Information classifies relaxation, dephasing, coherent error, leakage, erasure, correlation, and drift.
• Why Quantum Error Correction Is Possible explains correctability before platform-specific syndrome hardware is chosen.
• Quantum Teleportation supplies the primitive behind many modular and measurement-based architectures.
• Quantum Measurement as Estimation explains why every reported fidelity and hardware parameter is an inference with an estimand, likelihood, uncertainty, and calibration model.
• Control, Readout, and Calibration develops the closed loop from device models and waveform delivery through detector inference, validation, drift tracking, and feedback.
• Quantum Software Stack shows how a compiler and runtime consume a versioned hardware target rather than an undifferentiated device name.
• Circuit Intermediate Representations defines how target topology, native operations, timing, limits, and calibration epochs enter legalization without becoming source-level semantics.
• Qubit Mapping and Routing turns platform connectivity, operation direction, movement, timing, and resource constraints into an executable route.
• Error-Aware Compilation ranks legal executable candidates using versioned device evidence, uncertainty, context, and validation results.
• Superconducting Qubits applies the platform contract to transmons, flux circuits, microwave gates, dispersive readout, planar connectivity, cryogenic integration, and repeated error correction.
• Quantum Memories applies the same contract to write–store–read channels across optical, spin, oscillator, and error-corrected implementations.
• Interconnects and Transduction applies the contract to direct links, carrier conversion, added noise, temporal modes, heralded service rates, and modular evidence.
• Modular Architectures develops module contracts, stochastic resource supply, routing, distributed error correction, fault domains, and end-to-end system evidence.
• Cryogenic and Vacuum Infrastructure closes the environmental boundary through staged heat and noise ledgers, local gas loads, collision observables, diagnostics, and operating duty cycle.
• Materials and Fabrication Interface translates material, process, geometry, and assembly distributions into quantum-channel distributions, graph-aware yield, calibration burden, reliability, and architecture evidence.
• Quantum Information Roadmap places platform engineering after the formalism of states, measurements, circuits, noise, and correction.