Fault-Tolerant Quantum Computing Frontier

Status: repeated quantum error correction, logical-memory break-even, below-threshold scaling in several bounded experiments, fault-contained logical operations, magic-state preparation and distillation, and real-time decoding are established in specified devices and protocols. No architecture has yet combined all of these capabilities with enough logical qubits, circuit depth, throughput, yield, stability, and end-to-end validation for a useful general-purpose fault-tolerant computation. A winning architecture is not established.

Evidence cutoff: 11 August 2026. Processor records, code distances, logical error rates, decoder latency, and resource estimates are date-sensitive. Numerical projections remain conditional on their hardware, noise, decoder, compiler, and workload assumptions.

Core Question

Which complete architecture can turn noisy physical components into a useful logical computation at acceptable total cost?

The word complete matters. A fault-tolerant architecture is not just a code and not just a processor. It couples

$$\begin{aligned} \mathcal A_{\mathrm{FT}} =\{& \text{physical qubits and couplers},\, \text{code family},\, \text{syndrome circuit},\\ &\text{decoder and controller},\, \text{logical operations},\, \text{resource factories},\\ &\text{routing and memory},\, \text{compiler},\, \text{workload and verifier} \}. \end{aligned}$$

A strong result in one component is necessary evidence, but it does not establish the performance of the set $\mathcal A_{\mathrm{FT}}$. A code with excellent asymptotic rate may require unavailable connectivity. A processor with high-fidelity gates may not support repeated syndrome extraction. A logical memory may beat a physical reference yet lack a scalable non-Clifford gate. A resource estimate may count data patches while omitting factories, routing, spare qubits, calibration downtime, or classical processing.

The frontier therefore has four coupled questions:

1. Which architecture can scale to useful logical qubits?
2. What space, time, energy, and engineering overhead is acceptable?
3. How should memories and logical operations be benchmarked?
4. How can decoding, feedforward, calibration, and fault response run continuously?

Canonical Boundary

Why QEC Is Possible owns the error-correction conditions and threshold logic. Stabilizer Formalism owns stabilizer algebra. Surface Code owns planar patches, repeated extraction, detector geometry, thresholds, lattice-surgery geometry, and surface-code overhead. Fault-Tolerant Gates owns gadget correctness, error-spread containment, and the main protected logical-operation mechanisms. Decoders owns inference algorithms, calibrated priors, and real-time decoder evaluation. Error-Correction Case Studies audits implemented memories and logical demonstrations in detail.

This page has a different canonical role: it integrates those ingredients into a dated research map. Its subject is the gap between a bounded fault-tolerance demonstration and a sustained, useful fault-tolerant system.

Quantum Error Correction and Fault Tolerance supplies the stable canonical routing, protection record, and claim-class boundaries; this page retains the dated research landscape, contingent architecture comparisons, open bottlenecks, and update triggers.

An Evidence Ladder

Fault tolerance is not a binary label attached at the first appearance of a logical qubit. Evidence becomes stronger as more of the computation is included.

An evidence ladder for fault-tolerant quantum computing. Higher rungs inherit the requirements below them and add a new test. Provenance, stability, classical processing, and complete resource accounting run through every rung.

Rung 1: physical primitives

State preparation, entangling gates, idling, reset, and measurement are characterized under a declared operating condition. Component fidelities are important, but average gate fidelity alone does not specify leakage, crosstalk, correlated faults, coherent accumulation, or drift during a QEC cycle.

Rung 2: repeated syndrome extraction

Checks are measured for multiple rounds without destroying the encoded information. Detection events agree with a circuit-level model well enough to support decoding. This establishes an operating QEC circuit, not yet a beneficial logical channel.

Rung 3: fair logical break-even

The decoded logical memory outperforms a stated reference under comparable elapsed time, initialization, measurement, acceptance, and confidence. A comparison against one unusually poor physical qubit or against a shorter uncorrected experiment is not a fair break-even test.

Rung 4: below-threshold scaling

Logical failure decreases as code distance or another protection parameter increases while the physical operating point and decoding rules remain comparable. This is stronger than observing one protected device. It tests the direction of scaling, although only over the measured distance range and failure-rate window.

Rung 5: fault-contained logical operations

Logical preparation, measurement, Clifford gates, lattice surgery, teleportation, or another operation suppresses faults according to the code design. The benchmark must include the operation’s syndrome history and feedforward, not merely the fidelity of the final encoded state.

Rung 6: universal logical resource pipeline

The architecture supplies a universal set through magic states, code switching, gauge fixing, transversal constructions, or another declared mechanism. Preparation, verification, distillation, routing, consumption, and recovery operate at a throughput compatible with the logical circuit.

Rung 7: useful end-to-end computation

A workload of scientific or practical interest is compiled, executed, and validated with a complete failure budget and resource ledger. The comparison includes the strongest relevant classical method and the delivered cost of a correct answer, not just successful circuit time.

As of the evidence cutoff, experiments occupy several of the lower and middle rungs. Individual demonstrations have reached below-threshold memories, fault-tolerant logical gates, distilled magic states, real-time decoding, and multi-code universal primitives. The top rung has not been established.

What Is Established, and at What Scale?

The table deliberately separates a result from its extrapolation.

Capability	Established evidence	Boundary of the evidence
repeated QEC	many-cycle repetition, surface, color, small-block, and bosonic-code experiments	finite devices, finite distances, selected states, and finite observation windows
logical break-even	several memories outperform declared physical or uncorrected references	reference definitions differ; not every comparison includes equal time, yield, and hardware
below-threshold scaling	surface-code scaling through distance 7 on superconducting hardware; bounded scaling in color-code and neutral-atom experiments	a few distances do not determine the asymptotic regime or exclude a rare correlated-error floor
real-time decoding	integrated decoders have kept pace with repeated syndrome streams in bounded experiments	sustained throughput and tail latency at useful logical scale remain open
logical Clifford operations	demonstrated in trapped-ion, superconducting, neutral-atom, and other small-code processors	logical gate sets, code sizes, circuit depths, and protection levels remain limited
non-Clifford resources	fault-tolerant injection, logical magic-state preparation, and logical distillation have been demonstrated	factory yield, output rate, routing, and error at algorithmic scale are unresolved
architecture integration	processors have combined multiple code families, teleportation, logical entanglement, reset or reuse, and repeated correction	no experiment has sustained the full stack for a useful general-purpose workload

In a 2025 superconducting surface-code memory experiment, a distance-7 code using 101 qubits reached a reported logical error per cycle of $1.43(3)\times10^{-3}$ and a suppression factor of $2.14(2)$ when distance increased by two. A distance-5 experiment integrated a real-time decoder with an average latency of $63\,\mu\mathrm{s}$ over runs extending to one million cycles. These are major systems results. They do not by themselves supply logical gates, factories, routing, or useful algorithm depth.

Other architectures expose different pieces of the stack. Distance-3 to distance-5 color-code scaling, transversal Clifford benchmarking, magic-state injection, and lattice-surgery teleportation have been shown on a superconducting processor. Trapped-ion experiments have demonstrated fault-tolerant logical operations and a small-code universal gate set. Neutral-atom arrays have combined below-threshold tests, logical entanglement, transversal operations, lattice surgery, teleportation, several codes, and physical-qubit reuse in processors containing hundreds of atoms. Bosonic encodings have demonstrated repeated autonomous or concatenated protection, with noise bias and outer-code tradeoffs that differ sharply from two-level-qubit arrays.

These results are complementary, not entries in a single platform ranking. The experiments use different codes, noise structure, connectivity, acceptance rules, cycle times, logical observables, and reference channels.

Code Family and Hardware Are Different Choices

A hardware platform supplies physical states, interactions, measurement, reset, transport, and classical interfaces. A code family specifies which faults are detectable and how logical information is represented. The two choices constrain one another but should not be identified.

Architecture family	Principal opportunity	Dominant unresolved cost
local two-dimensional topological codes	bounded-weight checks, local connectivity, mature decoding and logical-routing constructions	low encoding rate, large spacetime volume, non-Clifford factories
color and small-block constructions	transversal operations or compact demonstrations; natural fit to some all-to-all devices	repeated extraction, concatenation or switching cost, scaling beyond small distance
high-rate quantum LDPC codes	many logical qubits per block and potentially much lower memory overhead	nonlocal or high-degree checks, logical operations, decoding, layout, and circuit-level realization
bosonic code plus outer code	correct or bias dominant oscillator faults before they reach the outer code	oscillator control, ancilla faults, residual uncorrected channels, universal operations
modular and distributed codes	independent modules, replaceable units, photonic links, and flexible scaling	link loss and fidelity, entanglement rate, buffering, synchronization, and network decoding

Surface codes remain a reference architecture because they match a common two-dimensional local-hardware constraint and have unusually mature tools. That does not prove that their overhead will be acceptable, nor that they will remain optimal when hardware connectivity, erasure information, bosonic encoding, or high-rate codes improve.

Quantum LDPC Codes make the rate question especially sharp. Bivariate-bicycle constructions have been analyzed with finite-rate, high-threshold, low-overhead memory layouts under a specified circuit-noise model. One representative comparison projected 12 logical qubits in 288 physical qubits where a surface-code construction required roughly 3000 under the authors’ matched target and assumptions. This is a theoretical architecture result, not a demonstrated universal processor. Check connectivity, syndrome circuits, logical access, decoder behavior under realistic faults, and fabrication constraints remain part of the cost.

Bosonic architectures alter the elementary unit. A cat code, binomial code, or Gottesman–Kitaev–Preskill encoding may suppress or reveal a dominant error before an outer code sees it. The gain is real only after counting oscillator modes, ancillary transmons or atoms, pumping and control hardware, cycle duration, and residual faults. In a 2025 concatenated cat-qubit experiment, phase-flip correction improved with repetition-code distance, while residual bit flips prevented the complete code from having the same asymptotic threshold interpretation. The result is valuable precisely because it identifies both the protected and unprotected channels.

Overhead Starts with a Failure Budget

“How many physical qubits per logical qubit?” is rarely the first resource question. An algorithm supplies a logical circuit with classes of locations: memory rounds, Clifford operations, non-Clifford resources, measurements, state preparations, communication steps, and classical decisions. If class $j$ contains $N_j$ opportunities for failure with effective logical error $p_{\mathrm L,j}$, a first-order budget is

$$P_{\mathrm{fail}} \lesssim \sum_j N_j p_{\mathrm L,j} +P_{\mathrm{prep}} +P_{\mathrm{read}} +P_{\mathrm{classical}}.$$

This union bound is conservative and ignores cancellation, but it is a useful audit. Assigning an allowance $\epsilon_j$ to class $j$ gives the approximate design condition

$$p_{\mathrm L,j}\lesssim\frac{\epsilon_j}{N_j}.$$

A circuit with $10^9$ relevant logical locations and a one-percent total failure allowance cannot be justified by a per-operation logical error near $10^{-6}$. A uniform allocation would ask for a scale near $10^{-11}$ before state preparation, readout, and classical failures are included. The exact allocation should reflect which faults are malignant and which observables the verifier accepts.

For a surface-code memory below threshold, a common engineering fit is

$$p_{\mathrm L}(d,p) \approx A\left(\frac{p}{p_{\mathrm{th}}}\right)^{(d+1)/2},$$

where $p$ is a physical error parameter, $p_{\mathrm{th}}$ is a threshold for a particular circuit and decoder, $d$ is distance, and $A$ is a fitted prefactor. Solving for the minimum odd distance gives

$$d \gtrsim 2\, \frac{\log\!\left(p_{\mathrm L}^{\star}/A\right)} {\log\!\left(p/p_{\mathrm{th}}\right)} -1.$$

For example, $A=0.1$, $p/p_{\mathrm{th}}=0.1$, and $p_{\mathrm L}^{\star}=10^{-12}$ imply $d\geq21$ within this model. The calculation is a conditional extrapolation, not a measured guarantee. It can fail if leakage, bursts, long-range correlations, fabrication defects, decoder mismatch, or drift introduce a floor.

Count every physical role

A useful qubit ledger is

$$\begin{aligned} N_{\mathrm{phys}}={}& N_{\mathrm{data}} +N_{\mathrm{syndrome}} +N_{\mathrm{factory}} +N_{\mathrm{route}}\\ &+N_{\mathrm{I/O}} +N_{\mathrm{spare}} +N_{\mathrm{service}}. \end{aligned}$$

The terms depend on the platform. Service resources may include cooling, readout resonators, optical modes, shuttling zones, communication qubits, or temporary ancillas. Some are not qubits but still constrain footprint, bandwidth, power, or yield. Reporting only $N_{\mathrm{data}}$ can miss the dominant term.

Count spacetime and throughput

Logical depth is not physical time. Let $\tau_{\mathrm{cycle}}$ be a QEC cycle time, $D_j$ the number of cycles needed for logical operation $j$, and $D_{\mathrm{idle}}$ the scheduled memory time. A baseline execution time is

$$T_{\mathrm{run}} =\tau_{\mathrm{cycle}} \left( D_{\mathrm{idle}}+\sum_j N_jD_j \right),$$

before compilation stalls, factory starvation, decoder backpressure, recalibration, restart, or verification are added.

Non-Clifford resources often set the pace. If each factory produces one accepted resource every $\tau_{\mathrm{fac}}$ cycles with yield $Y_T$, then $F$ parallel factories supply

$$R_{T,\mathrm{supply}} =\frac{F Y_T}{\tau_{\mathrm{fac}}}.$$

Avoiding starvation requires

$$R_{T,\mathrm{supply}} \geq R_{T,\mathrm{demand}},$$

including burst demand and routing latency. The corresponding factory qubits, buffers, failed batches, and verification measurements belong in the ledger. Magic-state demonstrations establish a resource transformation; a useful factory must also meet an error target and a schedule.

Count delivered answers

If a run is accepted with probability $p_{\mathrm{acc}}$ and an accepted run is correct with conditional probability $p_{\mathrm{corr}\mid\mathrm{acc}}$, then the probability of a correct delivered sample is

$$p_{\mathrm{del}} =p_{\mathrm{acc}}\, p_{\mathrm{corr}\mid\mathrm{acc}}.$$

For independent attempts with runtime $T_{\mathrm{run}}$, the mean time to one correct delivered sample is at least

$$\mathbb E[T_{\mathrm{del}}] \geq \frac{T_{\mathrm{run}}}{p_{\mathrm{del}}},$$

before queueing, diagnosis, and validation. Postselection can greatly improve conditional fidelity while making delivered throughput poor. Both quantities must be reported.

Resource Estimation Tools develops the complete estimation workflow. The frontier question is whether its assumptions can be tied to measured, sustained subsystem performance.

How to Compare Candidate Architectures

No scalar metric ranks a fault-tolerant architecture. A meaningful comparison holds the logical task and failure target fixed, then audits at least the following axes.

Axis	Questions
protection	What fault set and correlations are modeled? Is suppression measured versus distance?
rate	How many logical qubits are encoded per physical degree of freedom at the target error?
logical operations	Which operations are native, transversal, teleported, distilled, deformed, or switched?
connectivity	What physical interactions, transport, links, and scheduling conflicts are required?
classical loop	What syndrome bandwidth, decoder throughput, tail latency, memory, and calibration are required?
manufacturability	What yield, uniformity, repair, spare capacity, and control-line density are assumed?
delivery	What runtime, acceptance, restart, energy, and validation cost produces a correct answer?
evidence	Which entries are theorem, simulation, subsystem measurement, integrated experiment, or projection?

An architecture can trade one axis for another. Nonlocal connectivity may reduce code or routing overhead while making gates slower or less uniform. Erasure conversion can simplify decoding while requiring extra levels, ancillas, or detection operations. A high-rate memory block can encode many logical qubits yet make universal logical access difficult. Fast local gates can be neutralized by slow measurement. These are engineering tradeoffs, not contradictions.

The most informative comparison is a matched workload study:

1. fix the logical algorithm, precision, success condition, and verifier;
2. compile into each architecture’s allowed logical operations;
3. allocate the same total failure probability;
4. size codes and factories using architecture-specific measured or declared noise;
5. include routing, measurement, decoding, calibration, yield, and restart;
6. report sensitivity to uncertain inputs instead of one headline number.

A Benchmark Contract for Logical Operations

A logical gate error is not fully specified by the name of the gate and one fidelity. A benchmark should declare a contract.

Logical object

State the code, distance or block parameters, gauge, boundary convention, number of logical qubits, and whether the operation changes the code. A distance-$d$ memory and a distance-$d$ lattice-surgery operation do not have the same spacetime support.

Fault-tolerant circuit

Include preparation, check rounds, ancilla verification, feedforward, recovery or Pauli-frame update, leakage handling, and final readout. If a decoder uses future syndrome rounds, state the look-ahead and resulting latency.

Noise and operating point

Report physical error channels, crosstalk, leakage, loss, correlated events, drift, and calibration cadence. A result obtained after selecting unusually quiet intervals should identify that selection.

Metric and denominator

Specify logical failure per operation, per QEC cycle, per unit time, or per spacetime volume. Report separate logical $X$, $Y$, $Z$, leakage, and erasure components when bias matters. State whether failures are inferred from a fit, directly observed, or bounded with a confidence interval.

Acceptance and reference

Give unconditional performance and any postselected result, together with acceptance probability. Compare against a reference channel with the same elapsed time and task. For a logical two-qubit operation, useful references may include two independently protected memories, an unencoded operation, and the best declared physical implementation; each answers a different question.

Scaling test

Where possible, repeat the protocol at multiple distances or concatenation levels. A fault-tolerant circuit design constrains propagation; measured suppression tests whether the implemented fault distribution respects that design.

Reproducibility record

Archive circuit schedules, decoder version, calibration conditions, analysis code, sample counts, discarded shots, and uncertainty method. Reporting Standards provides the broader benchmark record.

Process tomography and randomized benchmarking can contribute, but each has limits. Full tomography scales poorly and can be distorted by preparation and measurement errors. Randomized protocols average over an ensemble and may hide rare, state-dependent, or temporally correlated logical faults. Direct algorithmic circuits test a relevant workload but mix gate, memory, compiler, and measurement errors. A mature benchmark program uses several views.

Decoding Is a Real-Time Systems Problem

Suppose $N_{\mathrm{check}}$ checks produce $b_{\mathrm{rec}}$ bits or bytes of raw record every cycle. The incoming syndrome bandwidth is approximately

$$B_{\mathrm{syn}} = \frac{N_{\mathrm{check}}b_{\mathrm{rec}}} {\tau_{\mathrm{cycle}}}.$$

One million checks, one raw bit per check, and a $1\,\mu\mathrm{s}$ cycle already imply $10^{12}$ bits per second before timestamps, confidence values, leakage flags, routing, or redundancy. Compression and locality can reduce transport, but the underlying events still have to be acquired and acted on.

Average decoding speed is not enough. If syndrome work arrives at rate $\lambda_{\mathrm{syn}}$ and the decoder services it at long-run rate $\mu_{\mathrm{dec}}$, a necessary stability condition is

$$\mu_{\mathrm{dec}}>\lambda_{\mathrm{syn}}.$$

Near equality, queueing delay and buffer occupancy become sensitive to bursts. The operational requirement is therefore a tail bound,

$$\Pr\!\left(T_{\mathrm{dec}}>T_{\mathrm{deadline}}\right) \leq \epsilon_{\mathrm{late}},$$

not only a mean latency. Windowed and parallel decoding can avoid an ever-growing backlog, while boundary reconciliation preserves consistency across windows. Sparse-matching implementations have demonstrated sub-round decoding time in specified simulation regimes, and integrated experiments have processed long streams in real time. Scaling must preserve accuracy, throughput, latency tails, and fault tolerance of the classical system itself.

A Pauli frame buys time, but not everywhere

Many inferred Pauli corrections need not be applied physically. They can be tracked in a Pauli frame and interpreted at later measurements. This decouples some decoder latency from the quantum cycle. It does not remove all deadlines. Adaptive measurements, non-Clifford injection, code deformation, qubit reuse, leakage response, and branch-dependent scheduling can require a classical decision before the next operation.

The benchmark should distinguish:

• acquisition latency from qubit to classical record;
• decoder compute latency;
• decision distribution and control latency;
• worst-case and high-quantile latency;
• deferred frame updates versus hard feedforward deadlines;
• behavior when the classical pipeline drops, delays, or corrupts a record.

Calibration Must Run with the Computation

Threshold arguments assume that the physical noise remains within an admissible region. Real devices drift. Interrupting a long computation for full recalibration may invalidate the stored logical state or dominate duty cycle, so calibration is part of the fault-tolerant control problem.

Syndrome data provide a natural diagnostic stream because detector statistics respond to physical-control errors. A 2026 superconducting experiment used reinforcement learning to tune more than 1000 control parameters from QEC detection events. It reported a factor-$2.4$ improvement in logical-error stability under injected drift, rising to $3.5$ when combined with decoder steering, and about 20% further logical-error suppression after conventional calibration. The hardware demonstrations used distance-5 and distance-7 surface codes and a distance-5 color code; scaling to distance 15 and tens of thousands of parameters was numerical.

This is evidence that calibration and QEC can share a closed loop. It does not yet show autonomous, unbiased control through a useful logical algorithm. The syndrome stream is also the decoder’s evidence, so adaptive calibration must avoid erasing rare faults, optimizing a proxy that is misaligned with logical failure, or introducing nonstationarity faster than the decoder model can follow. Independent holdout observables and injected-fault tests are essential.

Control, Readout, and Calibration owns the platform-level control chain. The frontier is its integration with encoded computation without stopping the machine or compromising the statistical record.

The Main Open Problems

Integrate memory and computation

Memory experiments are the cleanest place to test repeated correction, but an algorithm repeatedly changes stabilizers, consumes ancillas, moves information, and performs adaptive measurements. The resulting circuit has more boundaries and fault mechanisms than an idle logical patch.

The decisive scaling experiment is not simply a longer memory. It is a family of logical circuits whose error per useful operation decreases as protection increases, while the gate set, acceptance rule, and classical pipeline remain operationally comparable.

Resolve rare correlated faults and error floors

Below-threshold fits are often measured where logical failures are frequent enough to estimate. Useful algorithms demand rates many orders of magnitude lower. At that scale, rare bursts, radiation events, common-mode control errors, leakage cascades, decoder-model mismatch, and long-memory noise can dominate.

A simple floor model illustrates the issue:

$$p_{\mathrm L}(d) = A\Lambda^{-(d+1)/2} +p_{\mathrm{floor}}.$$

Increasing $d$ suppresses the first term but not $p_{\mathrm{floor}}$. Establishing a target near $10^{-12}$ therefore cannot rest only on a fit made near $10^{-3}$. It needs physical fault studies, accelerated tests, independent monitors, code families sensitive to different correlations, and long observation windows. A floor is not necessarily fundamental; it identifies a fault source that the present architecture does not suppress.

Make universal resources a production system

The Eastin–Knill theorem prevents a nontrivial exact finite-dimensional code from providing a universal set solely through transversal logical unitaries under its assumptions. Architectures add magic states, code switching, gauge fixing, teleportation, pieceable constructions, or other mechanisms.

The open problem is no longer whether such mechanisms exist. It is whether they can supply a large algorithm with:

• sufficiently low output error;
• adequate accepted-state throughput;
• bounded qubit and routing footprint;
• robust feedforward and frame management;
• tolerance to factory faults and outages;
• a verification record that catches correlated bad batches.

Parallel factories can reduce starvation but consume footprint and power. Larger distillation protocols can reduce output error but increase latency and sensitivity to correlated inputs. The optimal factory is workload- and architecture-dependent.

Magic State Distillation owns the established protocol mathematics, exact 15-to-1 map, factory failure modes, and bounded preparation-versus-distillation evidence. The open systems-integration milestone remains tracked here.

Reduce overhead without moving it off the ledger

High-rate codes, long-range coupling, biased-noise qubits, erasure conversion, transversal gates, and constant-overhead constructions can reduce a major term. Each can also transfer cost to connectivity, control, measurement, classical processing, or fabrication.

Theoretical advances have shown that fault-tolerant computation can achieve far better asymptotic overhead than early concatenated constructions under specified models. Recent proposals use high-rate codes, gauged logical operators, and transversal algorithmic constructions to improve space or time. The frontier is to turn those theorems into circuit-level architectures with local, noisy components and a credible implementation path.

Scale the classical co-processor

Decoding is only one classical workload. A full machine also performs pulse generation, readout discrimination, leakage classification, calibration, logical scheduling, factory management, fault logging, and verification. These tasks compete for bandwidth and may run at different temperature stages.

The classical system must itself fail rarely enough for the quantum failure budget. Silent corruption of a frame bit can become a logical error. A robust architecture needs redundancy, checksums or consistency tests, bounded recovery behavior, and a specification for what happens when a deadline is missed.

Sustain operation through drift, defects, and repair

A useful computation may run for hours, days, or longer. During that time, qubits can drift, links can fail, traps can empty, couplers can detune, and readout models can age. Code deformation and spare resources may route around defects, but adaptation must not create untracked logical transformations.

The relevant metric is not the best calibrated hour. It is the distribution of delivered logical performance over the planned mission time, including maintenance and recovery.

Demonstrate end-to-end utility

Fault tolerance is a means, not a workload. A useful demonstration must state the computational question, required precision, data-access cost, classical baseline, verification method, and wall-clock resource ledger. A small logical algorithm can be scientifically valuable as an integration test without establishing practical advantage. Calling those two claims by different names improves rather than diminishes the experiment.

Architecture Decisions That Remain Contingent

Locality versus rate

Two-dimensional local checks simplify hardware interactions and fault containment but tend to encode few logical qubits per area. High-rate codes improve encoding density but can demand longer-range, higher-degree, or time-multiplexed checks. Modular links create nonlocality through heralded entanglement, trading deterministic gates for link rate, loss handling, and buffers.

No universal locality budget exists. It must be evaluated against the actual platform’s interaction graph and error-versus-range curve.

Correction versus detection and restart

Error detection with postselection can be effective for shallow, high-value experiments. For long computations, acceptance can decay exponentially with the number of opportunities for rejection. Active correction preserves yield but demands more syndrome and control machinery. Hybrid strategies may detect severe events, correct routine events, and checkpoint selected classical information.

The decision should minimize delivered cost, not conditional error alone.

One large block versus many patches

A high-rate block can share syndrome resources and encode many logical qubits. Patch-based architectures offer modular placement, local surgery, and simpler failure isolation. Large blocks may make selective logical access and routing difficult; many patches may spend most qubits on boundaries and factories.

Workload interaction graphs and non-Clifford demand can reverse the preferred choice.

Hardware-tailored versus portable codes

Noise bias, erasure flags, native multi-qubit measurements, transport, and oscillator structure can substantially improve a tailored code. Tailoring can also make performance sensitive to an unstable noise feature. A mature design reports both the gain when the feature holds and the degradation when it does not.

What Would Change the Assessment?

The frontier should be updated when evidence crosses a durable boundary, not whenever a larger component count is announced. Strong update triggers include:

• reproducible logical-error suppression over several increasing code distances for both memory and a universal logical operation set;
• sustained real-time decoding and control at a syndrome rate and mission duration relevant to a declared useful workload;
• a complete magic-state or alternative universal-resource pipeline whose measured output error and throughput meet a compiled circuit’s demand;
• an experimentally grounded architecture comparison that includes data, ancillas, factories, routing, spares, calibration, classical processing, yield, and delivered runtime;
• direct constraints on rare correlated faults at or below the algorithmic failure target;
• a fault-tolerant computation of scientific interest with a transparent verifier and a competitive end-to-end classical comparison;
• repeated results across devices or groups using an interoperable logical benchmark contract.

A million physical qubits would not by itself meet any of these triggers. A smaller system could meet several.

Common Mistakes

Calling any encoded circuit fault tolerant

Encoding is not enough. Fault tolerance constrains preparation, syndrome extraction, logical operations, measurement, and classical response so that a small number of physical faults cannot spread into an uncontrolled logical failure.

Treating threshold as a hardware fidelity target

A threshold belongs to a code, extraction circuit, decoder, noise model, and metric. Comparing a component’s average fidelity with a quoted threshold from another model is not an architecture assessment.

Equating break-even with scalable suppression

One logical channel can beat one physical reference without logical error continuing to decrease at larger distance. Break-even and below-threshold scaling are separate rungs.

Comparing unlike logical error rates

Per-cycle, per-round, per-gate, per-unit-time, conditional, and unconditional rates have different denominators. Convert them only with an explicit model.

Ignoring acceptance and retry

Postselection can make the accepted subset excellent while the probability of delivery collapses. Always pair conditional performance with acceptance and wall-clock cost.

Counting only code qubits

Factories, routing, measurement ancillas, links, buffers, spares, and classical infrastructure may dominate. A logical-qubit ratio without roles is not a system estimate.

Assuming average decoder latency guarantees operation

A stable mean can hide a heavy tail or burst backlog. Report throughput, quantiles, deadlines, and recovery behavior.

Turning a record into a roadmap

A record is a measured point in a specific protocol. A roadmap extrapolates through unmeasured distances, fault rates, yields, and integration steps. Preserve that distinction.

Exercises

Exercise 1: Allocate a logical failure budget

A compiled workload contains $4\times10^8$ logical Clifford locations, $2\times10^7$ injected non-Clifford resources, and $10^6$ final logical measurements. Allocate a total failure allowance of $0.01$ in the proportions 40%, 40%, and 20%, respectively. What uniform error target applies within each class under the union-bound model?

Solution

The class allowances are

$$\epsilon_C=0.004,\qquad \epsilon_T=0.004,\qquad \epsilon_M=0.002.$$

Dividing by the number of locations gives

$$\begin{aligned} p_{\mathrm L,C} &\lesssim \frac{0.004}{4\times10^8} =10^{-11},\\ p_{\mathrm L,T} &\lesssim \frac{0.004}{2\times10^7} =2\times10^{-10},\\ p_{\mathrm L,M} &\lesssim \frac{0.002}{10^6} =2\times10^{-9}. \end{aligned}$$

The targets differ because the location counts differ. This allocation omits preparation, classical-control, and correlated failures, so a real design would reserve margin for them.

Exercise 2: Estimate a conditional code distance

Use

$$p_{\mathrm L} =0.1 \left(\frac{p}{p_{\mathrm{th}}}\right)^{(d+1)/2}$$

with $p/p_{\mathrm{th}}=0.1$. Find the smallest odd $d$ for which $p_{\mathrm L}\leq10^{-12}$. Name two reasons the estimate may fail.

Solution

The condition is

$$0.1(0.1)^{(d+1)/2}\leq10^{-12}.$$

Thus

$$1+\frac{d+1}{2}\geq12,$$

so $(d+1)/2\geq11$ and the smallest odd distance is $d=21$.

The estimate may fail if the fitted power law does not persist to such low rates, or if correlated faults, leakage, drift, fabrication defects, or decoder mismatch create an error floor. It also uses a memory-like fit that need not apply to every logical operation.

Exercise 3: Size the syndrome data path

A machine measures $1.5\times10^6$ checks every $800\,\mathrm{ns}$. Each check produces a two-byte record after local discrimination. Compute the raw record bandwidth. If the classical pipeline can sustain $3.0\,\mathrm{TB\,s^{-1}}$, does the mean-rate stability test pass?

Solution

The incoming record rate is

$$B_{\mathrm{syn}} = \frac{(1.5\times10^6)(2\,\mathrm{byte})} {8.0\times10^{-7}\,\mathrm{s}} =3.75\times10^{12}\,\mathrm{byte\,s^{-1}}.$$

That is $3.75\,\mathrm{TB\,s^{-1}}$ using decimal units, already above the stated $3.0\,\mathrm{TB\,s^{-1}}$ service rate. The queue is unstable even before metadata and bursts are included. Local compression or more distributed processing is required.

Exercise 4: Count magic-state factories

A factory outputs one accepted $T$ resource every 200 QEC cycles with yield $0.9$. A compiled layer consumes an average of one resource every 10 cycles. How many parallel factories are required by the mean-rate condition?

Solution

With $F$ factories,

$$R_{T,\mathrm{supply}} =\frac{0.9F}{200}$$

resources per cycle. The demand is $0.1$ per cycle, so

$$\frac{0.9F}{200}\geq0.1 \quad\Longrightarrow\quad F\geq22.22\ldots.$$

At least 23 factories are required. A practical design needs additional buffer or capacity because stochastic factory failures and burst demand can cause starvation even when mean rates match.

Exercise 5: Audit a break-even claim

An encoded memory survives for $2\,\mathrm{ms}$ with success probability $0.995$. It is compared with a physical qubit measured after $4\,\mathrm{ms}$ with success probability $0.990$. Is logical break-even established?

Solution

No. The elapsed times differ, so the two channels implement different memory tasks. The encoded result may be excellent, but a fair break-even claim needs the encoded and physical references evaluated over the same requested storage time, with compatible preparation, measurement, and uncertainty. Hardware count and acceptance should also be reported.

Exercise 6: Convert conditional fidelity into delivered time

A postselected logical circuit takes two hours per attempt, accepts 40% of runs, and produces the correct result in 99% of accepted runs. Assuming independent attempts and immediate diagnosis, what is the mean time to a correct delivered result?

Solution

The delivery probability per attempt is

$$p_{\mathrm{del}} =0.40\times0.99 =0.396.$$

The expected number of attempts is $1/0.396$, so

$$\mathbb E[T_{\mathrm{del}}] =\frac{2\,\mathrm{h}}{0.396} \approx5.05\,\mathrm{h}.$$

This excludes queueing, validation, recalibration, and any correlations between attempts.

Exercise 7: Diagnose a correlated-error floor

Measurements at increasing distance follow

$$p_{\mathrm L}(d) =0.08(0.45)^{(d+1)/2}+2\times10^{-7}.$$

Can increasing distance alone reach $10^{-9}$? What architectural conclusion follows?

Solution

No. The first term tends to zero, but

$$\lim_{d\to\infty}p_{\mathrm L}(d) =2\times10^{-7},$$

which is two hundred times the target. The architecture must identify and suppress the source represented by the floor, modify the code or fault model so that the source becomes correctable, or change the target workload. Increasing distance without addressing the floor only increases cost.

Exercise 8: Classify an architecture claim

A simulation of a high-rate code under independent circuit depolarizing noise projects one-tenth the physical-qubit count of a surface-code layout at a specified logical-memory target. Which conclusions are supported, and which are not?

Solution

The result supports a conditional comparative claim: under the specified noise, decoder, connectivity, circuit, target, and accounting rules, the simulated high-rate construction has lower modeled memory-qubit overhead.

It does not establish lower overhead on hardware, a universal logical gate set, acceptable measurement and routing cost, decoder performance under correlated faults, manufacturability, or lower end-to-end algorithm runtime. Those are separate entries in the architecture contract.

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Further Connections

• Threshold Theorem gives the conditional asymptotic result behind the evidence ladder and explains why finite-device scaling is not itself a universal threshold guarantee.
• Hardware Overview compares the physical modalities without treating one component metric as a system ranking.
• Metrics for Quantum Hardware defines fidelity, coherence, crosstalk, leakage, connectivity, speed, and yield metrics used at the bottom of the evidence ladder.
• Resource Estimation translates algorithmic demand and those hardware assumptions into explicit distance, qubit, factory, runtime, failure, and spacetime ledgers.
• Claims and Evidence Checklist supplies a reproducible procedure for auditing architecture and scaling claims.
• Negative Results and Limitations explains how no-go theorems, benchmark reversals, extrapolation failures, and resource bottlenecks should update a technology assessment.
• Quantum Software Stack connects logical resources to compilation, scheduling, execution, and verification.
• Modular Architectures develops link, entanglement-distribution, buffering, and synchronization costs for distributed fault tolerance.
• Common Noise Models distinguishes independent stochastic models from coherent, correlated, non-Markovian, leakage, and erasure processes.
• Quantum Information Roadmap places the frontier after channels, codes, logical operations, hardware, and validation.