Quantum LDPC and High-Rate Codes

Status: asymptotically good qLDPC codes, efficient decoders for selected families, finite blocks with favorable circuit-level simulations, and low-space-overhead fault-tolerance protocols are established theoretically under stated models. Repeated qLDPC syndrome extraction and multi-logical encoding have been demonstrated in small nonlocal hardware blocks. Below-threshold qLDPC scaling across increasing blocks, useful-scale real-time decoding, and a complete universal low-overhead hardware architecture are not established.

Evidence cutoff: 11 August 2026. Finite-code records, decoder comparisons, hardware layouts, and logical-operation protocols are rapidly changing. Preprints and simulations are labeled by evidence type rather than promoted to hardware results.

Core Question

Can high-rate sparse quantum codes reduce the delivered cost of reliable logical computation after every displaced resource is counted?

The attraction is straightforward. A surface-code patch usually encodes one logical qubit in $\Theta(d^2)$ data and syndrome qubits. A constant-rate qLDPC block can encode $k=\Theta(n)$ logical qubits while retaining bounded-weight checks, and an asymptotically good family can also have $d=\Theta(n)$. In the code model, this permits constant physical-qubit overhead per logical qubit as the target computation grows.

The frontier begins after that statement. Nonlocal Tanner edges, extraction ancillas, correlated logical failures, decoder post-processing, logical addressability, resource-state preparation, and hardware yield can consume the apparent gain. The three durable research questions are:

1. Can high-rate codes reduce finite-size, end-to-end overhead substantially?
2. Which decoding strategies remain accurate and timely as blocks and noise models scale?
3. Can hardware realize the required sparse but nonlocal connectivity without losing the code advantage?

Canonical Boundary

Quantum LDPC Codes owns the qLDPC definition, CSS and Tanner-graph algebra, hypergraph products, modern product constructions, decoding foundations, and syndrome-circuit language. Surface Code owns the geometrically local reference architecture. Fault-Tolerant Quantum Computing Frontier owns the cross-architecture evidence ladder and complete system failure budget.

This page owns the dated frontier assessment: whether qLDPC’s rate and distance advantages survive finite blocks, physical circuits, decoding, layout, logical operations, and delivered-workload accounting.

The Resource-Transfer Test

A claim of “ten times lower overhead” is incomplete until the denominator and omitted resources are named.

The qLDPC resource-transfer test. A rate or distance gain at the code layer becomes a system advantage only if finite blocks, syndrome circuits, hardware embedding, decoding and control, and logical operations preserve it. Each stage can add space, time, error, or postselection cost.

Suppose a block encodes $k$ logical qubits in $n$ data qubits. To hold $Q$ logical qubits, the idealized data count is

$$N_{\mathrm{data}} = n\left\lceil\frac{Q}{k}\right\rceil.$$

For large $Q$, its data overhead approaches $n/k=1/R$. The effective spatial overhead is instead

$$\omega_{\mathrm{space}} = \frac{ N_{\mathrm{data}} +N_{\mathrm{check}} +N_{\mathrm{route}} +N_{\mathrm{buffer}} +N_{\mathrm{spare}} +N_{\mathrm{factory}} }{Q_{\mathrm{served}}},$$

where $Q_{\mathrm{served}}$ excludes logical qubits reserved for routing, distillation, verification, or recovery. A high-rate memory can lose its advantage if one check ancilla per row, several communication qubits per edge, or many auxiliary blocks are required.

Time enters through the physical syndrome cycle,

$$\tau_{\mathrm{QEC}} = \tau_{\mathrm{prep}} +\tau_{\mathrm{interact}} +\tau_{\mathrm{route}} +\tau_{\mathrm{measure}} +\tau_{\mathrm{classical}},$$

with overlaps counted rather than simply summed when operations are pipelined. A lower qubit count paired with a much longer cycle can increase logical error per unit time and wall-clock workload cost.

One useful system metric is logical service density,

$$\mathcal S = \frac{ Q_{\mathrm{served}} \left(1-P_{\mathrm{block}}\right) Y_{\mathrm{acc}} }{ N_{\mathrm{physical}}\tau_{\mathrm{QEC}} },$$

where $Y_{\mathrm{acc}}$ is the fraction of cycles or runs retained. This is not a universal benchmark, but it exposes the terms that a rate-only ratio omits.

What the Asymptotic Breakthrough Settled

The 2022 construction of asymptotically good qLDPC codes settled an existence question:

$$k=\Theta(n), \qquad d=\Theta(n), \qquad w,\Delta=O(1)$$

can hold simultaneously.

That result rules out the idea that stabilizer commutation inherently forces either vanishing rate or sublinear distance for every qLDPC family. It also provides a theoretical foundation for constant-space-overhead fault tolerance.

It did not settle:

• useful finite block lengths and constants;
• the best code family below a few thousand qubits;
• circuit-level thresholds with realistic correlated noise;
• decoder accuracy and latency at algorithmic target rates;
• a manufacturable connectivity graph;
• individually addressable logical operations;
• the best space–time overhead for a compiled workload.

The open frontier is therefore not “Do good qLDPC codes exist?” It is “Which good or nearly good finite codes form a better machine?”

Finite Blocks Decide the First Crossover

Asymptotic order can be misleading at moderate size. Let architecture $A$ be a high-rate qLDPC block and $B$ a collection of surface-code patches. A finite crossover occurs only when both meet the same logical service target:

$$\begin{aligned} P_{\mathrm{fail}}^{(A)} &\leq\epsilon, & P_{\mathrm{fail}}^{(B)} &\leq\epsilon,\\ T_{\mathrm{del}}^{(A)} &\leq T^\star, & T_{\mathrm{del}}^{(B)} &\leq T^\star. \end{aligned}$$

The comparison should then minimize physical footprint, energy, or another declared cost. Matching only $n$, $k$, and abstract $d$ is insufficient.

Useful finite-code questions

For each candidate block:

• Is distance proved, certified, or only heuristically estimated?
• Are $X$ and $Z$ distances balanced for the measured noise?
• How many checks are independent, and how much redundancy is available?
• What are the maximum check diameter and edge-length distribution?
• Does the extraction circuit preserve the intended circuit distance?
• At what physical error does the block beat a matched local-code reference?
• Does that crossover persist when idle, routing, leakage, and crosstalk faults are added?
• How are logical failures correlated across the $k$ encoded qubits?

A large $k/n$ with weak distance can be useful for shallow error detection but poor for a long fault-tolerant workload. A lower-rate block with cleaner extraction and stronger subthreshold scaling can win at the target error.

Block failure versus marginal failure

For logical events $L_1,\ldots,L_k$,

$$P_{\mathrm{block}} = \Pr\!\left(\bigcup_{j=1}^k L_j\right) \leq \sum_{j=1}^k\Pr(L_j).$$

If each marginal failure is $p_{\mathrm{marg}}$ and correlations are weak, $P_{\mathrm{block}}\approx kp_{\mathrm{marg}}$ at small error. A high-rate block therefore needs a lower marginal rate to maintain a fixed probability that no logical qubit fails. Correlated multi-logical events can make the relation better or worse than an independence model for a particular observable.

Report at least:

• block failure;
• marginal failure distribution;
• logical-weight distribution of failures;
• covariance or another multi-logical correlation summary;
• which logical basis and states were tested.

The Current Finite-Size Reference Point

Bivariate-bicycle codes became influential because they supplied more than good asymptotic language. They supplied explicit moderate blocks, weight-6 checks, a depth-7 idealized extraction schedule, degree-6 connectivity decomposable into two planar layers, and circuit-level decoding.

A representative 2024 study analyzed a $[[144,12,12]]$ memory with 144 data and 144 check ancillas. Under its standard circuit-level depolarizing model and decoder, it reported a threshold around $0.7\%$ in the version of record and projected preservation of 12 logical qubits for nearly one million cycles at physical error $0.1\%$. Its matched estimate used 288 physical qubits, compared with roughly 3000 for surface-code patches.

This is strong architecture evidence because code, circuit, decoder, and connectivity were specified together. It remains a simulation-based projection. The threshold and crossover can move under long-range-gate penalties, idle noise, leakage, fabrication defects, decoder mismatch, or a different logical-service target.

The appropriate conclusion is neither “qLDPC has solved overhead” nor “the comparison is irrelevant until millions of qubits exist.” It is that a specific, falsifiable finite architecture now exists for hardware and decoder tests.

Which Decoders Can Scale?

There is no single qLDPC decoding problem. The decoder input can be one perfect syndrome, repeated noisy syndromes, detector events from a full circuit, erasure locations, soft readout values, or a learned detector model. Its output may be needed only for final interpretation or before an adaptive logical operation.

A decoder claim should be represented by a performance vector:

$$\mathcal D = \left( P_{\mathrm L},\, \mu_{\mathrm{throughput}},\, T_{50},\, T_{99.9},\, M_{\mathrm{classical}},\, E_{\mathrm{classical}} \right),$$

where $P_{\mathrm L}$ is logical failure, $\mu_{\mathrm{throughput}}$ is sustained service rate, $T_q$ is a latency quantile, and the last terms are memory and energy use. The best logical error at unlimited runtime and the best real-time decoder are different optimization points.

The syndrome load scales with blocks

If each block emits $m$ check records every $\tau_{\mathrm{QEC}}$ and $B$ blocks operate concurrently, the raw record rate is

$$\lambda_{\mathrm{record}} = \frac{Bm}{\tau_{\mathrm{QEC}}}.$$

Constant check density means $m=\Theta(n)$, so total classical load is linear in protected hardware size. Linear scaling is necessary but not sufficient: the coefficient, data movement, post-processing, and latency tails must fit the control system.

BP+OSD is a baseline, not an endpoint

Belief propagation with ordered-statistics decoding is the most common general finite-size baseline for hypergraph-product and bivariate-bicycle codes. BP exploits sparse Tanner edges; OSD repairs inconsistent or poor BP decisions. Its strengths are broad applicability and competitive logical accuracy. Its weaknesses include short-cycle sensitivity and a post-processing cost whose tail can become large.

A fair report specifies BP schedule, damping, iteration count, OSD order, timeout, and whether $X$–$Z$ correlations are modeled. Saying “decoded with BP+OSD” is not enough to reproduce a result.

Localization controls combinatorics

Localized-statistics decoding identifies connected or nearby syndrome clusters, solves smaller reliability-ranked problems, and merges their corrections. A 2025 circuit-level study of the $[[144,12,12]]$ bivariate-bicycle code reported a threshold near $0.7\%$ and parallelizable performance while avoiding global high-order OSD on every instance.

The unresolved question is robustness when clusters percolate, noise is correlated, checks are missing, or a hardware defect joins regions that were assumed independent.

Search width trades latency for accuracy

A 2026 beam-search decoder used BP to guide a bounded set of candidate partial corrections. On studied bivariate-bicycle circuits, beam width tuned an explicit accuracy–runtime tradeoff. The paper reported 99.9-percentile latencies below $1\,\mathrm{ms}$ for one configuration relevant to slower trapped-ion cycles, on a single CPU core.

This is useful real-time evidence in software simulation. It does not imply sub-microsecond decoding for superconducting cycles, nor does one bivariate-bicycle benchmark establish all-code scaling.

Learned decoders need an out-of-distribution contract

Graph neural networks and learned message passing share weights over a sparse graph and can scale more naturally than a dense model. Training can adapt to correlated circuit noise. The risk is distribution shift:

• device drift;
• code size or boundary changes;
• new leakage mechanisms;
• rare bursts absent from training;
• decoder-induced blind spots in the calibration signal.

A learned decoder needs holdout devices or time windows, injected-fault tests, uncertainty or abstention behavior, a fallback path, and latency measurement on the target classical hardware.

Provable and empirical scaling answer different questions

Quantum expander and Tanner-code decoders have proofs for correcting large adversarial sets under expansion and local-code hypotheses. Those proofs establish algorithmic scaling and fault tolerance. Finite BP, localized, and search decoders may perform better on a particular stochastic circuit without the same theorem.

The frontier needs both:

1. provable families showing that accurate scalable inference is possible;
2. finite implementations showing that constants and noise mismatch are acceptable.

Can Hardware Realize the Connectivity?

A qLDPC Tanner graph has $O(n)$ edges and bounded degree. It does not require all-to-all connectivity. It generally does require a sparse set of edges that cannot all be short in a single two-dimensional Euclidean layer when rate and distance are both strong.

An implementation should publish a connectivity ledger:

$$\mathcal G_{\mathrm{hw}} = \left\{ L_e,\, N_{\mathrm{layer}},\, N_{\mathrm{cross}},\, D_{\mathrm{route}},\, P_{\mathrm{parallel}},\, \varepsilon_e(L_e) \right\},$$

where $L_e$ is the edge-length distribution, $N_{\mathrm{layer}}$ the routing-layer count, $N_{\mathrm{cross}}$ a crossing or transition measure, $D_{\mathrm{route}}$ routing depth, $P_{\mathrm{parallel}}$ usable parallelism, and $\varepsilon_e(L_e)$ the error-versus-range relation.

Fixed multilayer superconducting layouts

Bivariate-bicycle connectivity can be partitioned into a small number of planar subgraphs, motivating flip-chip, crossover, resonator, and multilayer coupler proposals. In 2026 a hardware-aware placement and routing study generated roughly 150 explicit layouts across several qLDPC families. Its HAL heuristic quantified routing tiers, long-edge lengths, bump transitions, and through-silicon-via use rather than declaring nonlocality abstractly.

That work made the embedding problem reproducible. It assumed a multilayer stack and abstracted detailed qubit-cell design, coupler fidelity, crosstalk, frequency crowding, control wiring, and fabrication yield. A routed graph is not yet a calibrated processor.

Also in 2026, a 32-transmon processor with overlapping long-range couplers measured all weight-6 checks of two small qLDPC blocks repeatedly. This established that nonlocal sparse extraction can be built and operated. The reported logical error per logical qubit per cycle remained several percent, so the experiment did not yet demonstrate qLDPC break-even or scaling.

Reconfigurable atom arrays

Neutral atoms can convert graph nonlocality into motion or long-range Rydberg gates. Product structure can support parallel row and column operations, and atom loss can provide erasure information. Architecture studies have projected finite-size qLDPC crossovers at hundreds of atoms under their movement and circuit models.

The physical ledger must include:

• rearrangement distance and duration;
• atom loss and replacement;
• heating and dephasing during motion;
• range-dependent Rydberg-gate error;
• simultaneous-gate crosstalk;
• measurement and reload zones;
• decoder deadlines relative to slower cycles.

Reconfigurability changes the locality tradeoff; it does not make transport free.

Trapped ions

All-to-all reachability within an ion chain and shuttling between zones can realize nonlocal check graphs with few swaps. Slower entangling and measurement cycles relax decoder deadlines. Shared motional modes, spectator errors, transport heating, and limited parallelism then become central.

A 2024 nonlocal trapped-ion experiment entangled four logical qubits in one finite-rate block beyond its declared physical comparison. It was an important demonstration of multi-logical organization and transversal operation, not a scaling result for asymptotically good codes.

Modular and photonic routes

Distributed modules can realize Tanner edges through heralded Bell pairs or fusion operations. Failed links may be located erasures rather than hidden Pauli faults. The costs are entanglement-generation rate, buffers, synchronization, link ancillas, and decoding across missing or delayed checks.

The best qLDPC graph for a modular machine may be one whose expansion and partition structure match the network, not the code with the largest abstract rate.

Memory Is Not Yet Computation

High-rate memories protect many logical qubits compactly. A useful processor must also prepare, measure, entangle, route, and apply a universal gate set without destroying that compactness.

Logical addressability

In a surface-code layout, a patch boundary provides a geometric handle on one logical qubit. In a high-rate block, logical Pauli supports can overlap and extend across the same data qubits. An operation intended for logical qubit $j$ must avoid uncontrolled action on the other $k-1$ logical coordinates.

Code automorphisms and transversal operations can act on many logical qubits efficiently but may provide only a subgroup of the desired transformations. Changing logical basis can turn a simple operation into a dense one.

Measurement-based logical operations

Gauging a logical Pauli operator, generalized code surgery, and teleportation can convert a desired logical measurement into a set of sparse checks on an expanded code. Recent theory has reduced the additional qubit cost to nearly linear in logical-operator weight for broad code classes.

The frontier questions are finite:

• What circuit distance is preserved?
• How many auxiliary qubits and rounds are needed?
• Can many logical measurements run in parallel?
• Does the decoder support the changing check graph?
• How are long operators embedded in hardware?

Constant-overhead fault tolerance

Several recent protocols combine constant-rate qLDPC blocks with state preparation, teleportation, or code surgery to obtain constant spatial overhead and polylogarithmic or improved time overhead under stated models. 2026 work also developed parallelized code surgery and locally testable resource-state preparation for good qLDPC codes.

These are major theoretical advances. Their asymptotic overhead guarantees do not yet provide a finite universal machine specification. Required local codes, auxiliary states, expansion constants, classical decoding, and connectivity must be instantiated.

Transversal logical families

Another 2026 construction provided qLDPC families supporting broad Clifford operations through transversal structure and simulated depth-126 logical circuits under circuit noise. This directly attacks the memory–computation gap. It remains a code-and-simulation result rather than an implemented low-overhead processor.

Non-Clifford resources remain necessary for universal computation unless a different code-switching or injection mechanism is supplied. Factory and routing costs must be added to the memory rate.

Evidence Map as of August 2026

Claim	Current status	Strongest evidence type	Missing step
asymptotically good qLDPC codes exist	established	theorem and explicit construction families	practical constants are separate
qLDPC can have finite memory overhead far below matched surface-code estimates	established conditionally	end-to-end circuit simulation for explicit blocks	hardware scaling under matched noise and time
generic qLDPC decoding can be practical	developing	finite circuit simulations, parallel algorithms, CPU latency studies	sustained target-hardware throughput and robustness
sparse nonlocal checks can be implemented	established at small scale	repeated 32-qubit superconducting qLDPC experiment; nonlocal trapped-ion blocks	below-threshold scaling over increasing blocks
nonlocal qLDPC graphs can be physically laid out	developing	explicit multilayer and reconfigurable-layout studies	fabricated yield, calibrated edge errors, crosstalk
constant-space-overhead qLDPC computation is possible	established in models	fault-tolerance theorems and logical-operation constructions	finite compiled architecture and experiment
qLDPC has lower delivered cost for a useful algorithm	not established	conditional resource estimates	end-to-end logical hardware benchmark

The evidence is no longer purely asymptotic. It is also not yet a system demonstration. That middle status is the defining feature of the present frontier.

Open Problems

Find finite families, not isolated records

A useful family needs several blocks with increasing protection, compatible connectivity, known logical bases, and a common decoder. Optimizing one $[[n,k,d]]$ instance can produce a record that has no clean successor.

The search objective should include

$$\Phi = \alpha\frac{k}{n} +\beta\frac{d}{n} -\gamma w -\zeta C_{\mathrm{embed}} -\xi C_{\mathrm{decode}},$$

with coefficients tied to a hardware and workload model. Maximizing $k$ or $d$ alone is not enough.

Measure range-dependent and correlated faults

Long couplers, global beams, shared modes, transport operations, and photonic links create fault structure unlike independent nearest-neighbor depolarizing noise. A qLDPC code’s nonlocal graph can either disperse a local hardware fault or align with a common-mode event.

Experiments need detector correlations conditioned on:

• edge length and routing layer;
• simultaneous-gate pattern;
• movement distance or motional mode;
• coupler crossings and shared controls;
• leakage and loss;
• calibration age;
• cosmic-ray or burst monitors.

A decoder trained on independent faults can turn model mismatch into a logical error floor.

Co-design decoder and control without circular validation

The syndrome stream can update both the logical frame and physical calibration. If the same learned model controls the device and scores its performance, it may suppress the diagnostics that reveal its own mistakes. Holdout detectors, periodic blind tests, injected faults, and independent logical observables are needed.

Make hardware yield part of code selection

A high-rate block may be sensitive to a few missing long edges. Code puncturing, graph repair, spare couplers, and rerouting can preserve function, but each changes distance and decoder behavior. The code-design loop should output a distribution over fabricated devices, not one perfect graph.

Benchmark logical operations at the same protection level

A memory round, a transversal gate, a gauged measurement, and a teleportation step expose different spacetime regions. Claims that gates perform “near memory” should use matched distance, elapsed time, decoder, acceptance, and logical observables. Multi-logical correlation is especially important when one operation acts across a high-rate block.

Establish a delivered-workload crossover

The strongest demonstration would compile the same nontrivial logical workload into a qLDPC architecture and a mature local-code architecture, allocate the same failure budget, and execute or emulate every physical and classical stage with measured parameters. The result should report physical qubits, qubit-time, energy, acceptance, wall-clock time, and verifier cost.

What Would Change the Assessment?

Strong update triggers include:

• hardware logical-error suppression across at least three increasing qLDPC blocks under comparable circuits and decoding;
• a qLDPC logical memory that beats a matched local-code reference in both physical footprint and elapsed-time-normalized performance;
• sustained decoding at target syndrome bandwidth with reported 99.9- or 99.99-percentile latency and fault recovery;
• a fabricated nonlocal layout whose measured edge-error and crosstalk distributions support the projected circuit threshold;
• a universal logical operation set on one scalable qLDPC family with measured distance preservation and accepted throughput;
• an end-to-end resource estimate grounded in measurements from all major subsystems, with sensitivity analysis and reproducible compilation;
• independent reproduction of a finite-block crossover on another device or platform.

A higher asymptotic exponent, a larger simulated block, or a new decoder record is valuable but does not alone establish a system crossover.

Common Mistakes

Treating constant rate as constant total overhead

Constant $n/k$ concerns data in an abstract block. Extraction ancillas, routing, logical operations, factories, and spares can scale differently.

Calling sparse connectivity local

Bounded degree means $O(n)$ edges, not short edges. A constant-degree expander cannot be embedded in a plane with every edge short and every crossing free.

Comparing one qLDPC block with one surface-code patch

A high-rate block protects many logical qubits. Compare it with enough patches to protect the same number at the same total failure and elapsed time.

Using abstract distance as the benchmark denominator

Two codes with distance 12 can have different circuit distance, extraction depth, thresholds, and logical prefactors. Distance is a constraint, not a complete performance prediction.

Quoting mean decoder latency

Adaptive operations fail on missed deadlines in the tail. Report quantiles, timeouts, backlog behavior, and what the controller does on failure.

Ignoring multi-logical correlations

A block can have low average marginal error while rare events damage many logical qubits at once. Algorithms care about the resulting failure pattern.

Promoting a layout to an experiment

Placement and routing establish geometric feasibility under design rules. They do not measure coupler fidelity, crosstalk, yield, or calibration burden.

Promoting a memory theorem to a universal architecture

Low-overhead storage does not supply preparation, arbitrary logical measurements, non-Clifford resources, routing, or workload verification.

Exercises

Exercise 1: Compute effective spatial overhead

Ten $[[144,12,12]]$ blocks serve 120 logical data qubits. Each block uses 144 check ancillas and 24 routing or buffer qubits. The design reserves 10% spare capacity on the subtotal. Compute the total physical count and effective physical qubits per served logical qubit.

Solution

Each block uses

$$144+144+24=312$$

physical qubits before spares. Ten blocks use 3120. Ten-percent spare capacity adds 312, so

$$N_{\mathrm{physical}}=3432.$$

The effective overhead is

$$\omega_{\mathrm{space}} =\frac{3432}{120} =28.6$$

physical qubits per served logical qubit. The abstract data ratio $n/k=12$ would have missed more than half the implemented footprint.

Exercise 2: Convert marginal to block failure

A block encodes 12 logical qubits. Assume independent marginal logical failure $p=10^{-6}$ per cycle. Compute the probability that at least one logical qubit fails in a cycle and its small-$p$ approximation.

Solution

Independence gives

$$P_{\mathrm{block}} =1-(1-p)^{12}.$$

For $p=10^{-6}$,

$$P_{\mathrm{block}} \approx1.1999934\times10^{-5}.$$

The first-order approximation is $12p=1.2\times10^{-5}$. Correlated logical faults would invalidate the independence calculation, which is why the logical-weight distribution should be measured.

Exercise 3: Size decoder throughput

Five hundred blocks each emit 144 check records every millisecond. What record rate must the decoder sustain? If measured service capacity is $8.0\times10^7$ records per second, what fractional mean-rate margin remains?

Solution

The incoming rate is

$$\lambda = \frac{(500)(144)}{10^{-3}\,\mathrm{s}} =7.2\times10^7\,\mathrm{s}^{-1}.$$

The fractional margin relative to arrival is

$$\frac{8.0-7.2}{7.2} \approx0.111,$$

or about 11%. Mean stability passes, but such a small margin may still produce large queues under bursts or heavy-tailed post-processing.

Exercise 4: Interpret a latency quantile

A decoder has median latency $0.2\,\mathrm{ms}$ and $T_{99.9}=0.8\,\mathrm{ms}$. The QEC cycle is $1\,\mathrm{ms}$, but an adaptive logical measurement needs a decision within $0.5\,\mathrm{ms}$. Is the decoder shown to meet the hard deadline?

Solution

No. Being faster than the cycle at the 99.9th percentile does not establish a $0.5\,\mathrm{ms}$ deadline. The report must give

$$\Pr(T_{\mathrm{dec}}>0.5\,\mathrm{ms})$$

and compare it with the logical failure budget. Deferred Pauli-frame updates may tolerate the slower tail, but the stated adaptive measurement cannot.

Exercise 5: Include cycle time in a crossover

A qLDPC design uses 288 physical qubits for 12 logical qubits with a $10\,\mu\mathrm{s}$ syndrome cycle. A matched surface-code estimate uses 3000 qubits with a $1\,\mu\mathrm{s}$ cycle. Compute physical-qubit microseconds per cycle for each. What does the comparison show?

Solution

The qLDPC qubit-time per cycle is

$$(288)(10\,\mu\mathrm{s}) =2880\ \text{qubit-}\mu\mathrm{s}.$$

The surface-code value is

$$(3000)(1\,\mu\mathrm{s}) =3000\ \text{qubit-}\mu\mathrm{s}.$$

The tenfold footprint reduction becomes only a small qubit-time reduction in this simplified comparison. This does not decide which architecture wins: the cycles may have different logical error, logical work, energy, and parallelism. It shows why cycle duration belongs in the ledger.

Exercise 6: Account for postselection

A logical preparation has conditional failure $10^{-5}$ and acceptance $0.25$. It takes $4\,\mathrm{ms}$ per attempt. What is the mean accepted-state production rate, ignoring queueing, and what is the probability that an attempt delivers a correct accepted state?

Solution

The attempt rate is $250\,\mathrm{s}^{-1}$. Multiplying by acceptance gives

$$R_{\mathrm{acc}} =62.5\,\mathrm{s}^{-1}.$$

The correct-delivery probability per attempt is

$$p_{\mathrm{del}} =0.25(1-10^{-5}) =0.2499975.$$

The low conditional failure does not imply high throughput; three quarters of attempts are discarded.

Exercise 7: Diagnose a routing transfer

A code reduces data qubits by a factor of eight relative to a local-code baseline. Its implementation requires one check ancilla per data qubit, routing qubits equal to twice the data count, and 25% spares on all three roles. What is the implemented count in units of the qLDPC data count, and what maximum reduction remains?

Solution

Let qLDPC data count be $N$. Before spares,

$$N_{\mathrm{subtotal}} =N+N+2N =4N.$$

Adding 25% spares gives $5N$. The local baseline data count was $8N$, so at most

$$\frac{8N}{5N}=1.6$$

fold spatial reduction remains before the baseline’s own ancillas and spares are counted. Most of the nominal factor of eight moved into implementation roles.

Exercise 8: Classify a 2026 claim

A peer-reviewed paper gives explicit multilayer routes for 150 qLDPC code graphs and reports routing-layer and edge-length metrics, but fabricates no processor. Which frontier claim does it support?

Solution

It supports a design- and simulation-level claim that those graphs can be embedded under the paper’s multilayer routing rules with quantified geometric cost. It strengthens hardware feasibility and code–layout co-design.

It does not establish fabrication yield, calibrated long-coupler fidelity, crosstalk, syndrome-cycle error, logical suppression, or delivered overhead. Those require device measurements and integrated QEC experiments.

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Further Connections

• Quantum LDPC Codes provides the stable algebra, construction, decoding, and circuit foundations behind this dated assessment.
• Error-Correction Case Studies supplies the benchmark ladder for repeated syndromes, break-even, and below-threshold hardware scaling.
• Resource Estimation Tools turns finite code, decoder, connectivity, and logical-operation assumptions into sensitivity-tested system estimates.
• Control, Readout, and Calibration develops the physical–classical loop that must sustain qLDPC syndrome throughput.
• Modular Architectures develops link, buffer, synchronization, and fault-domain costs for distributed Tanner graphs.
• Reporting Standards gives the reproducibility record for decoder, layout, postselection, and finite-code comparisons.
• Negative Results and Limitations explains how locality bounds, error floors, and failed crossovers should narrow architecture claims.